DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet
DSPIC33FJ12MC201-I/SO
Specifications of DSPIC33FJ12MC201-I/SO
Related parts for DSPIC33FJ12MC201-I/SO
DSPIC33FJ12MC201-I/SO Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Digital Signal Controllers Preliminary DS70265B ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... FIFO on each capture • Output Compare ( channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Interrupt Controller: • 5-cycle latency • 118 interrupt vectors • available interrupt sources • external interrupts • ...
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... Motor Control Peripherals: • 6-channel 16-bit Motor Control PWM - 3 duty cycle generators - Independent or Complementary mode - Programmable dead time and output polarity - Edge-aligned or center-aligned - Manual output override control - 1 Fault input - Trigger for ADC conversions - PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned ...
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... PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. dsPIC33FJ12MC201/202 Controller Families Program Flash Device Pins Memory (Kbyte) (Kbyte) dsPIC33FJ12MC201 20 12 dsPIC33FJ12MC202 28 12 Note 1: Only 2 out of 3 timers are remappable. ...
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... SDIP/SSOP Package Diagram 20-PIN SDIP 20-PIN SSOP PGD2/EMUD2/AN0/V PGC2/EMC2/AN1/V PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 dsPIC33FJ12MC202 28-Pin SDIP/SOIC Package Diagram 28-PIN SDIP 28-PIN SOIC PGD2/EMUD2/AN0/V PGC2/EMUC2/AN1/V PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5/CN27/RB5 DS70265B-page 4 V MCLR ...
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... QFN Package Diagram 28-Pin QFN 6x6 mm PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 V SS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM1L2/RP13/CN13/RB13 1 21 PWM1H2/RP12/CN14/RB12 TMS/PWM1L3/RP11/CN15/RB11 dsPIC33FJ12MC202 4 18 TDI/PWM1H3/RP10/CN16/RB10 DDCORE TDO/PWM2L1/SDA1/RP9/CN21/RB9 Preliminary DS70265B-page 5 ...
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... Table of Contents dsPIC33FJ12MC201/202 Product Families ........................................................................................................................................... 3 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU ............................................................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 23 4.0 Flash Program Memory .............................................................................................................................................................. 49 5.0 Resets ....................................................................................................................................................................................... 55 6.0 Interrupt Controller ..................................................................................................................................................................... 61 7.0 Oscillator Configuration .............................................................................................................................................................. 93 8.0 Power-Saving Features ............................................................................................................................................................ 103 9.0 I/O Ports ................................................................................................................................................................................... 105 10.0 Timer1 ...................................................................................................................................................................................... 129 11.0 Timer2/3 feature ...................................................................................................................................................................... 131 12 ...
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... Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ12MC201/ 202 family of devices. Table 1-1 lists the functions of the latest the various pins shown in the pinout diagrams. ...
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... FIGURE 1-1: dsPIC33FJ12MC201/202 BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks Power-up ...
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... CMOS Position Up/Down Counter Direction State. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Analog = Analog input ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type I ST PWM1 Fault A input. FLTA1 O — PWM1 Low output 1 PWM1L1 O — PWM1 High output 1 PWM1H1 O — PWM1 Low output 2 PWM1L2 O — PWM1 High output 2 PWM1H2 O — PWM1 Low output 3 ...
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... CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ12MC201/202 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Special MCU Features The dsPIC33FJ12MC201/202 features a 17-bit by 17- bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1 ...
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... FIGURE 2-2: dsPIC33FJ12MC201/202 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 D15 D0 W0/WREG W10 W11 W12/DSP Offset ...
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... CPU Control Registers REGISTER 2-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (2) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 OA: Accumulator A Overflow Status bit ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (2) Preliminary DS70265B-page 15 ...
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... REGISTER 2-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...
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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 17 ...
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... Arithmetic Logic Unit (ALU) The dsPIC33FJ12MC201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...
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... FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70265B-page 19 ...
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... MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... Microchip Technology Inc. dsPIC33FJ12MC201/202 into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: • ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... Manual (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the dsPIC33FJ12MC201/202 devices is shown in Figure 3-1. dsPIC33FJ12MC201/202 0x000000 GOTO Instruction 0x000002 ...
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... A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. dsPIC33FJ12MC201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...
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... Data Address Space The dsPIC33FJ12MC201/202 CPU has a separate 16- bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
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... FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES WITH 1 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x09FF 0x0A01 1 Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70265B-page 26 LSB 16 bits Address MSb LSb ...
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... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 27 ...
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TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC201 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 — ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 3-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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... POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L P1DC1 01D6 P1DC2 01D8 P1DC3 01DA Legend uninitialized bit, — = unimplemented, read as ‘0’ TABLE 3-9: 4-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ12MC201 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — ...
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TABLE 3-10: 2-OUTPUT PWM2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P2TCON 05C0 PTEN — PTSIDL — P2TMR 05C2 PTDIR P2TPER 05C4 — P2SECMP 05C6 SEVTDIR PWM2CON1 05C8 — — — — PWM2CON2 05CA ...
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TABLE 3-13: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 3-15: ADC1 REGISTER MAP FOR dsPIC33FJ12MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... TABLE 3-16: ADC1 REGISTER MAP FOR dsPIC33FJ12MC201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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TABLE 3-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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... TABLE 3-19: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12MC201 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR2 06C4 — — — — RPOR3 06C6 — — — RPOR4 06C8 — — — RPOR6 06CC — ...
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TABLE 3-23: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ12MC201/202 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4 ...
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... Individual instruc- tions may support different subsets of these addressing modes. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...
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... MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary the difference between the © 2007 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 3.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • ...
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... TABLE 3-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70265B-page 44 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal © 2007 Microchip Technology Inc. ...
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... Interfacing Program and Data Memory Spaces The dsPIC33FJ12MC201/202 architecture uses a 24- bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70265B-page 46 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2007 Microchip Technology Inc. ...
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... TBLPAG © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2007 Microchip Technology Inc. ...
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... Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ12MC201/202 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming ...
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... RTSP Operation The dsPIC33FJ12MC201/202 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. Table 23-12 shows typical erase and programming times ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) U-0 U-0 — — (1) U-0 R/W-0 R/W-0 — ...
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... REGISTER 4-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Satiable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY< ...
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... W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000 Perform the TBLWT instructions to write the latches ...
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... RESETS Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters ...
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... REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1> POR (RCON<0>) Note: All Reset flag bits can be set or cleared by the user software. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) (CONTINUED) Setting Event Trap conflict event Illegal opcode or uninitialized W register access Configuration mismatch MCLR Reset ...
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... Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 7.0 “Oscillator Configuration” for further details. ...
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... FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... NOTES: DS70265B-page 60 Preliminary © 2007 Microchip Technology Inc. ...
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... Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. dsPIC33FJ12MC201/202 devices implement unique interrupts and 4 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. ...
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... FIGURE 6-1: dsPIC33FJ12MC201/202 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... Microchip Technology Inc. dsPIC33FJ12MC201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... TABLE 6-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 0x000088 67 59 ...
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... Interrupt Control and Status Registers dsPIC33FJ12MC201/202 devices implement a total of 22 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 6.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources ...
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... REGISTER 6-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits ...
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... Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
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... REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘ ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — U-0 ...
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... REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 71 ...
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... REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit ...
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... Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — QEIIF U-0 ...
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... REGISTER 6-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10 FLTA2IF: PWM2 Fault A Interrupt Flag Status bit ...
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... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — ...
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... REGISTER 6-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70265B-page 76 Preliminary © 2007 Microchip Technology Inc. ...
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... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — U-0 ...
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... REGISTER 6-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 U-0 FLTA1IE — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit 1 = Interrupt request enabled ...
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... Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — FLA2IE U-0 U-0 U-0 — ...
Page 82
... REGISTER 6-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 83
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-1 — — ...
Page 84
... REGISTER 6-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 85
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — — R/W-0 U-0 R/W-1 — ...
Page 86
... REGISTER 6-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 87
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 88
... REGISTER 6-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-1 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 89
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 90
... REGISTER 6-21: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 R/W-1 R/W-0 — FLTA1IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 91
... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — ...
Page 92
... REGISTER 6-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • ...
Page 93
... ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 94
... NOTES: DS70265B-page 92 Preliminary © 2007 Microchip Technology Inc. ...
Page 95
... Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters. The dsPIC33FJ12MC201/202 oscillator provides: • External and internal oscillator options as clock sources FIGURE 7-1: dsPIC33FJ12MC201/202 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSCO S3 OSCI S1 FRC Oscillator TUN<5:0> ÷ 16 LPRC Oscillator Secondary Oscillator SOSCO ...
Page 96
... CPU Clocking System The dsPIC33FJ12MC201/202 devices provide seven system clock options: • Fast RC (FRC) Oscillator • FRC Oscillator with PLL • Primary (XT EC) Oscillator • Primary Oscillator with PLL • Secondary (LP) Oscillator • Low-Power RC (LPRC) Oscillator • FRC Oscillator with postscaler 7 ...
Page 97
... MHz, which is within the 100-200 MHz ranged needed. • If PLLPOST<1:0> then This provides a Fosc of 160 MHz. The resultant device operating speed is 80 MIPS. FIGURE 7-2: dsPIC33FJ12MC201/202 PLL BLOCK DIAGRAM Source (Crystal, External Clock PLLPRE or Internal RC) Divide by TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION ...
Page 98
... REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 99
... OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 97 ...
Page 100
... REGISTER 7-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 101
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 102
... REGISTER 7-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Center frequency +11 ...
Page 103
... Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ12MC201/202 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD< ...
Page 104
... NOTES: DS70265B-page 102 Preliminary © 2007 Microchip Technology Inc. ...
Page 105
... Clock Frequency and Clock Switching dsPIC33FJ12MC201/202 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON< ...
Page 106
... IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 107
... I/O PORTS Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters ...
Page 108
... DS70265B-page 106 9.3 Input Change Notification The input change notification function of the I/O ports allows the dsPIC33FJ12MC201/202 devices to gener- ate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device ...
Page 109
... These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In ...
Page 110
... FIGURE 9-2: REMAPPABLE MUX INPUT FOR U1RX RP0 RP1 RP2 RP15 TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer 2 External Clock Timer 3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A ...
Page 111
... SS1OUT OC1 OC2 UPDN © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of 00000 technique ...
Page 112
... Peripheral Mapping The control schema of peripheral select pins is not limited to a small range of fixed configurations. There are no mutual or hardware- enforced lockouts between any of the peripheral mapping SFRs. Literally any combination of peripheral mappings across any or all of the RPn pins is possible. ...
Page 113
... Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 EXAMPLE 9-2: //************************************* // Unlock Registers //************************************* asm volatile ( "mov #OSCCONL, w1 ...
Page 114
... Peripheral Pin Select Registers The dsPIC33FJ12MC201/202 family implement 21 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (13) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON[IOLOCK See Section 9.4.4.1 “Control Register Lock” for a specific command sequence. ...
Page 115
... INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R<4:0> ...
Page 116
... REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR< ...
Page 117
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 118
... REGISTER 9-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R< ...
Page 119
... FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> ...
Page 120
... REGISTER 9-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 FLTA2R< ...
Page 121
... QEA1R<4:0>: Assign A(QEA) to the corresponding pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 R/W-1 QEA1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 122
... REGISTER 9-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INDX1R< ...
Page 123
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ...
Page 124
... REGISTER 9-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R< ...
Page 125
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS1R< ...
Page 126
... REGISTER 9-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R< ...
Page 127
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
Page 128
... REGISTER 9-18: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R< ...
Page 129
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
Page 130
... NOTES: DS70265B-page 128 Preliminary © 2007 Microchip Technology Inc. ...
Page 131
... TIMER1 Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters ...
Page 132
... REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 133
... TIMER2/3 FEATURE Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters ...
Page 134
... FIGURE 11-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 135
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70265B-page 133 ...
Page 136
... REGISTER 11-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2 Stops 32-bit Timer2/3 ...
Page 137
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 (1) — — R/W-0 U-0 (1) — ...
Page 138
... NOTES: DS70265B-page 136 Preliminary © 2007 Microchip Technology Inc. ...
Page 139
... Reference chapters. The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33FJ12MC201/202 devices support up to eight input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1 ...
Page 140
... Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 141
... OUTPUT COMPARE Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters ...
Page 142
... Pulse-Width Modulation Mode Use the following steps when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected Timer Period register (PRy). 2. Set the PWM duty cycle by writing to the OCxRS register. 3. Write the OxCR register with the initial duty cycle. ...
Page 143
... Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: OCFA pin controls OC1-OC2 channels. 3: TMR2/TMR3 can be selected via OCTSEL (OCxCON<3>) bit. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 61 Hz 122 Hz 977 ...
Page 144
... REGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 145
... Family Reference chapters. The dsPIC33FJ12MC201/202 device supports up to two dedicated Pulse Width Modulation (PWM) modules. The PWM1 module is a 6-channel PWM generator, and the PWM2 module is a 2-channel PWM generator. The PWM module has the following features: • 16-bit resolution • ...
Page 146
... FIGURE 14-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM Enable and Mode SFRs PWM1CON2 P1DTCON1 Dead-Time Control SFRs P1DTCON2 Fault Pin Control SFRs P1FLTACON PWM Manual P1OVDCON Control SFR P1TMR Comparator P1TPER P1TPER Buffer P1TCON Comparator P1SECMP PWM Time Base Note: Details of PWM Generator #1and #2 not shown for clarity ...
Page 147
... P2FLTACON PWM Manual P2OVDCON Control SFR P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM Generator # 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM2H1 ...
Page 148
... PWM Time Base The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the P TMR SFR. P TMR<15> read-only status X X bit, PTDIR, that indicates the present count direction of the PWM time base. ...
Page 149
... A write to the P TCON register X • Any device Reset The P TMR register is not cleared when P X written. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.4 PWM Period P TPER is a 15-bit register used to set the counting X TMR register X period for the PWM time base. P buffered register ...
Page 150
... FIGURE 14-3: EDGE-ALIGNED PWM New Duty Cycle Latched PxTPER P TMR X Value 0 Duty Cycle Period 14.6 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Count mode (see Figure 14-4). The PWM compare output is driven to the active state ...
Page 151
... PxDC1 register controls PWM1H/PWM1L outputs • PxDC2 register controls PWM2H/PWM2L outputs • PxDC3 register controls PWM3H/PWM3L outputs © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Complementary mode is selected for each PWM pin pair by clearing the appropriate PMODx bit in the PWMxCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device Reset ...
Page 152
... FIGURE 14-5: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Time Selected by DTSxA bit ( 14.9.2 DEAD-TIME ASSIGNMENT The PxDTCON2 SFR contains control bits that allow the dead times to be assigned to each of the comple- mentary outputs. Table 14-1 summarizes the function of each dead-time selection control bit ...
Page 153
... PWMxH pin in the pair. Dead-time insertion is still performed when PWM channels are overridden manually. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.12.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMxCON2 register is set, all output overrides performed via the PxOVDCON register are synchronized to the PWM time base ...
Page 154
... FAULT PIN ENABLE BITS The PxFLTACON SFR have four control bits that deter- mine whether a particular pair of PWM I/O pins controlled by the Fault input pin. To enable a specific PWM I/O pin pair for Fault overrides, the corresponding bit should be set in the PxFLTACON register. ...
Page 155
... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Count mode. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.16.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS< ...
Page 156
... REGISTER 14-1: PxTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 PTEN — PTSIDL bit 15 R/W-0 R/W-0 R/W-0 PTOPS<3:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on ...
Page 157
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ...
Page 158
... REGISTER 14-4: PxSECMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 (1) SEVTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit Special Event Trigger will occur when the PWM time base is counting downward ...
Page 159
... Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only 1 PWM I/O pin pair. PWM1 on dsPIC33FJ12MC201 devices supports only two PWM I/O pin pairs. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 ...
Page 160
... REGISTER 14-6: PWMxCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 1111 = 1:16 postscale • ...
Page 161
... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA< ...
Page 162
... REGISTER 14-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — DTS3A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5 DTS3A: Dead-Time Select for PWM3 Signal Going Active bit ...
Page 163
... PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H FAOV2L ...
Page 164
... REGISTER 14-10: PxOVDCON: OVERRIDE CONTROL REGISTER U-0 U-0 R/W-1 — — POVD3H bit 15 U-0 U-0 R/W-0 — — POUT3H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits ...
Page 165
... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC2<15:0>: PWM Duty Cycle #2 Value bits © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 166
... REGISTER 14-13: P1DC3: PWM DUTY CYCLE REGISTER 3 R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle #3 Value bits DS70265B-page 164 R/W-0 R/W-0 R/W-0 PDC3<15:8> ...
Page 167
... QUADRATURE ENCODER INTERFACE (QEI) MODULE Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) ...
Page 168
... Quadrature Encoder Interface Logic A typical incremental (or optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, the direction of the motor is deemed positive or for- ward ...
Page 169
... QEI to timer or vice versa) will not affect the Timer/Position Count register contents. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 The UPDN control/status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer counts up. When UPDN = 0, the timer counts down. In addition, control bit UPDN_SRC, (in QEICON< ...
Page 170
... TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in Idle mode and the QEI mod- ule is configured in 16-bit Timer mode, the 16-bit timer will operate if QEISIDL (QEICON<13> This bit defaults to a logic ‘0’ upon executing POR. To halt the timer module during CPU Idle mode, QEISIDL should be set to ‘ ...
Page 171
... Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R-0 R/W-0 R/W-0 INDEX UPDN R/W-0 ...
Page 172
... REGISTER 15-1: QEICON: QEI CONTROL REGISTER (CONTINUED) bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit Timer mode only) bit 2 POSRES: Position Counter Reset Enable bit ...
Page 173
... Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — IMV<2:0> U-0 U-0 — ...
Page 174
... NOTES: DS70265B-page 172 Preliminary © 2007 Microchip Technology Inc. ...
Page 175
... SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for ...
Page 176
... SPI Setup: Slave Mode To set up the SPI module for the Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFSn register. b) Set the SPIxIE bit in the respective IECn register. c) Write the SPIxIP bits in the respective IPCn register to set the interrupt priority ...
Page 177
... SPIxBUF. FIGURE 16-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F FIGURE 16-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb MSb ...
Page 178
... FIGURE 16-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM dsPIC33F FIGURE 16-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK TABLE 16-1: SAMPLE SCKx FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note: SCKx frequencies shown in kHz ...
Page 179
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — ...
Page 180
... REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12 ...
Page 181
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 179 ...
Page 182
... REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 183
... INTER-INTEGRATED CIRCUIT Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for dsPIC33F Family Reference chapters ...
Page 184
... FIGURE 17-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70265B-page 182 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 185
... Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 17.8 General Call Address Support The general call address can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledgement ...
Page 186
... Slope Control 2 The I C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user application to disable slew rate control if desired necessary to disable the slew rate control for 1 MHz mode. ...
Page 187
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 188
... REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit 2 (when operating Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit ...
Page 189
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/C-0 HS — — R/C-0 HSC ...
Page 190
... REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 191
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
Page 192
... NOTES: DS70265B-page 190 Preliminary © 2007 Microchip Technology Inc. ...
Page 193
... Reference chapters. The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33FJ12MC201/202 device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and ® ...
Page 194
... UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The BRGx register controls the period of a free-running 16-bit timer. Equation 18-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 18-1: ...
Page 195
... Write 0x55 to UxTXREG, which loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 18.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 18.2 “ ...
Page 196
... REGISTER 18-1: UxMODE: UART R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 197
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 MODE REGISTER (CONTINUED) x Preliminary DS70265B-page 195 ...
Page 198
... REGISTER 18-2: U STA: UART x R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use ...
Page 199
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS70265B-page 197 ...
Page 200
... NOTES: DS70265B-page 198 Preliminary © 2007 Microchip Technology Inc. ...