PIC16F88-I/SO Microchip Technology, PIC16F88-I/SO Datasheet - Page 96
![IC MCU FLASH 4KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F88-I/SO
Manufacturer Part Number
PIC16F88-I/SO
Description
IC MCU FLASH 4KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F87-IP.pdf
(228 pages)
5.PIC16F87-IP.pdf
(8 pages)
6.PIC16F87-IP.pdf
(4 pages)
7.PIC16F87-IP.pdf
(8 pages)
8.PIC16F88-ISO.pdf
(214 pages)
Specifications of PIC16F88-I/SO
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Data Rom Size
256 B
A/d Bit Size
10 bit
A/d Channels Available
7
Height
2.31 mm
Length
11.53 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F88-I/SO
Manufacturer:
ROHM
Quantity:
15 000
Part Number:
PIC16F88-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- PIC16F87-IP PDF datasheet #7
- PIC16F88-ISO PDF datasheet #8
- Current page: 96 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
6.1
6.2
DS31006A-page 6-2
Introduction
Program Memory Organization
There are two memory blocks in the Section 6. Memory Organization; program memory and data
memory. Each block has its own bus, so that access to each block can occur during the same
oscillator cycle.
The data memory can further be broken down into General Purpose RAM and the Special Func-
tion Registers (SFRs). The operation of the SFRs that control the “core” are described here. The
SFRs used to control the peripheral modules are described in the section discussing each indi-
vidual peripheral module.
Mid-Range MCU devices have a 13-bit program counter capable of addressing an 8K x 14 pro-
gram memory space. The width of the program memory bus (instruction word) is 14-bits. Since
all instructions are a single word, a device with an 8K x 14 program memory has space for 8K of
instructions. This makes it much easier to determine if a device has sufficient program memory
for a desired application.
This program memory space is divided into four pages of 2K words each (0h - 7FFh, 800h -
FFFh, 1000h - 17FFh, and 1800h - 1FFFh).
as the 8 level deep hardware stack. Depending on the device, only a portion of this memory may
be implemented. Please refer to the device data sheet for the available memory.
To jump between the program memory pages, the high bits of the Program Counter (PC) must
be modified. This is done by writing the desired value into a SFR called PCLATH (Program
Counter Latch High). If sequential instructions are executed, the program counter will cross the
page boundaries without any user intervention. For devices that have less than 8K words,
accessing a location above the physically implemented address will cause a wraparound. That
is, in a 4K-word device accessing 17FFh actually addresses 7FFh. 2K-word devices (or less) do
not require paging.
Figure 6-1
shows the program memory map as well
1997 Microchip Technology Inc.
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