PIC16F870-I/SS Microchip Technology, PIC16F870-I/SS Datasheet - Page 168

• Manufacturer Part Number: PIC16F870-I/SS
• Description: IC MCU FLASH 2KX14 EE 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F870-I/SS

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 28 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F871 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC164020 - MODULE SKT PROMATEII 44TQFPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / Rohs Status: Details

PIC16F870/871
U
Universal Synchronous Asynchronous Receiver Transmitter.
USART ................................................................................ 61
DS30569B-page 166
See USART
Address Detect Enable (ADDEN Bit) .......................... 62
Asynchronous Mode ................................................... 66
Asynchronous Receive ............................................... 68
Asynchronous Receive (9-bit Mode) ........................... 70
Asynchronous Receive with Address Detect.
Asynchronous Reception ............................................ 69
Asynchronous Transmitter .......................................... 66
Baud Rate Generator (BRG)....................................... 63
Clock Source Select (CSRC Bit) ................................. 61
Continuous Receive Enable (CREN Bit) ..................... 62
Framing Error (FERR Bit) ........................................... 62
Overrun Error (OERR Bit) ........................................... 62
Receive Data, 9th bit (RX9D Bit) ................................ 62
Receive Enable, 9-bit (RX9 Bit) .................................. 62
Serial Port Enable (SPEN Bit)............................... 61, 62
Single Receive Enable (SREN Bit) ............................. 62
Synchronous Master Mode ......................................... 72
Synchronous Master Reception .................................. 74
Synchronous Master Transmission............................. 72
Synchronous Slave Mode ........................................... 76
Synchronous Slave Reception .................................... 77
Synchronous Slave Transmit ...................................... 76
Transmit Data, 9th Bit (TX9D)..................................... 61
Transmit Enable (TXEN Bit)........................................ 61
Transmit Enable, Nine-bit (TX9 Bit) ............................ 61
Transmit Shift Register Status (TRMT Bit).................. 61
See Asynchronous Receive (9-bit Mode).
Baud Rate Formula............................................. 63
Baud Rates, Asynchronous Mode
Baud Rates, Asynchronous Mode
High Baud Rate Select (BRGH Bit)..................... 61
Sampling ............................................................. 63
(BRGH = 0) ................................................. 64
(BRGH = 1) ................................................. 65
W
Wake-up from SLEEP................................................. 87, 100
Watchdog Timer
Watchdog Timer (WDT)................................................ 87, 99
Write Verify
WWW, On-Line Support ....................................................... 4
Interrupts .................................................................... 93
MCLR Reset ............................................................... 93
Timing Diagram ........................................................ 101
WDT Reset ................................................................. 93
Register Summary ...................................................... 99
Enable (WDTEN Bit)................................................... 99
Postscaler. See Postscaler, WDT.
Programming Considerations ..................................... 99
RC Oscillator............................................................... 99
Time-out Period .......................................................... 99
WDT Reset, Normal Operation............................. 91, 93
WDT Reset, SLEEP.............................................. 91, 93
Data EEPROM and FLASH Program Memory ........... 31
 2003 Microchip Technology Inc.