PIC16F88-I/SS Microchip Technology, PIC16F88-I/SS Datasheet - Page 94
![IC MCU FLASH 4KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F88-I/SS
Manufacturer Part Number
PIC16F88-I/SS
Description
IC MCU FLASH 4KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F87-IP.pdf
(228 pages)
5.PIC16F87-IP.pdf
(8 pages)
6.PIC16F87-IP.pdf
(4 pages)
7.PIC16F87-IP.pdf
(8 pages)
8.PIC16F88-ISO.pdf
(214 pages)
Specifications of PIC16F88-I/SS
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Data Rom Size
256 B
A/d Bit Size
10 bit
A/d Channels Available
7
Height
1.75 mm
Length
7.2 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
5.3 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F88-I/SS
Manufacturer:
U-BLOX
Quantity:
12 000
PIC16F87/88
10.3
The SSP module in I
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RB4/
SCK/SCL pin, which is the clock (SCL) and the RB1/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISB<4,1> bits.
EXAMPLE 10-1:
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON<5>).
FIGURE 10-5:
The SSP module has five registers for I
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer register (SSPBUF)
• SSP Shift register (SSPSR) – Not directly
• SSP Address register (SSPADD)
DS30487C-page 92
MOVF
IORLW
ANDLW
MOVWF
RB4/SCK/
SCL
RB1/
accessible
SDA
SDI/
module
SSP I
TRISC, W
0x18
B’11111001’
TRISC
Read
Clock
Shift
2
implements
C Mode Operation
MSb
2
C mode fully implements all slave
SSP BLOCK DIAGRAM
(I
Stop Bit Detect
SSPADD Reg
SSPBUF Reg
Match Detect
SSPSR Reg
2
Start and
C™ MODE)
; Example for an 18-pin part such as the PIC16F818/819
; Ensures <4:3> bits are ‘11’
; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
the
LSb
standard
Write
Set, Reset
S, P Bits
(SSPSTAT Reg)
2
Addr Match
C operation:
Internal
Data Bus
mode
To ensure proper communication of the I
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
I
of the port containing the I
are changed in software during I
using a Read-Modify-Write instruction (BSF, BCF), then
the I
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I
using the instruction BSF or BCF during I
tion. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISB bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
Additional information on SSP I
found in the “PICmicro
Reference Manual” (DS33023).
2
C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>)
Stop bit interrupts enabled to support Firmware
Controlled Master mode
Stop bit interrupts enabled to support Firmware
Controlled Master mode
with Start and Stop bit interrupts enabled; slave is
Idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address) with Start and
C Slave mode (10-bit address) with Start and
C Firmware Controlled Master mode operation
2
C mode may stop functioning properly and I
2
C module.
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
2005 Microchip Technology Inc.
®
2
C pins (PORTx [SDA, SCL])
Mid-Range MCU Family
2
C operation may be
2
C communication
2
2
C Slave mode,
C communica-
2
C opera-
2
C pins)
2
C