ATMEGA16A-AU Atmel, ATMEGA16A-AU Datasheet - Page 180
![MCU AVR 16K FLASH 16MHZ 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16A-AU
Manufacturer Part Number
ATMEGA16A-AU
Description
MCU AVR 16K FLASH 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16A-AU
Manufacturer:
HIROSE
Quantity:
3 000
Part Number:
ATMEGA16A-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA16A-AUR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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ATmega16A
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing Masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several Masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 20-8. Arbitration between Two Masters
Note that arbitration is not allowed between:
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
• A REPEATED START condition and a data bit
• A STOP condition and a data bit
• A REPEATED START and a STOP condition
Synchronized
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
Arbitration, SDA
Master A Loses
A
SDA
8154B–AVR–07/09
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