DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F3012-30I/P
• Description: IC DSPIC MCU/DSP 24K 18DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F3012-30IP

Figure 35-6:
35.3.3
© 2008 Microchip Technology Inc.
SS1
SCK Input
(CKP = 0
CKE = 1)
SCK Input
(CKP = 1
CKE = 1)
SDO
Output
SDI Input
(SMP = 0)
Input
Sample
(SMP = 0)
SPI1IF
SPITBF
SPIRBF
Note 1: Operation for 8-bit mode is shown; the 16-bit mode is similar.
(2,3)
Write to
SPI1BUF
2: The SS1 pin must be used for Slave mode operation when CKE = 1.
3: When the SSEN (SPI1CON1<7>) bit is set to ‘1’, the SS1 pin must be driven low to enable transmission and
4: Transmit data is held in SPI1TXB and SPITBF remains set until all bits are transmitted.
(4)
Framed SPI Modes
reception in Slave mode.
SPI1 Slave Mode Timing (CKE = 1)
Section 35. Serial Peripheral Interface (SPI) (Part II)
The SPI1 module supports a basic framed SPI protocol while operating in either Master or Slave
modes. The module uses four control bits to configure framed SPI operation:
• FRMEN (SPI1CON2<15>) enables the Framed SPI modes and causes the SS1 pin to be
• SPIFSD (SPI1CON2<14>) determines whether the SS1 pin is an input or an output (i.e.,
• FRMPOL (SPI1CON2<13>) selects the polarity of the frame synchronization pulse
• FRMDLY (SPI1CON2<1>) selects whether the synchronization pulse coincides with or
used as a frame synchronization pulse input or output pin. The state of SSEN
(SPI1CON1<7>) is ignored.
whether the module receives or generates the frame synchronization pulse).
(active-high or active-low) for a single SPI data frame.
precedes the first serial clock pulse.
bit 7
bit 7
bit 6
bit 5
(1)
bit 4
bit 3
bit 2
SPI1SR to
SPI1RXB
bit 1
bit 0
bit 0
DS70272B-page 35-15
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