PIC24FJ64GA102-I/ML Microchip Technology, PIC24FJ64GA102-I/ML Datasheet - Page 170
![IC MCU 16BIT 64KB FLASH 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ64GA102-I/ML
Manufacturer Part Number
PIC24FJ64GA102-I/ML
Description
IC MCU 16BIT 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(308 pages)
2.PIC24FJ32GA102-ISP.pdf
(12 pages)
3.PIC24FJ32GA102-ISP.pdf
(48 pages)
4.PIC24FJ64GA104-IML.pdf
(300 pages)
Specifications of PIC24FJ64GA102-I/ML
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, LIN, SPI, USART
No. Of Pwm Channels
5
Embedded Interface Type
I2C, LIN, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA102-I/ML
Manufacturer:
MAXIM
Quantity:
15 620
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GA102-ISP PDF datasheet #3
- PIC24FJ64GA104-IML PDF datasheet #4
- Current page: 170 of 300
- Download datasheet (5Mb)
PIC24FJ64GA104 FAMILY
FIGURE 15-3:
FIGURE 15-4:
DS39951B-page 168
Note
PROCESSOR 1 (SPI Enhanced Buffer Master)
Note
1:
2:
1:
2:
PROCESSOR 1 (SPI Master)
MSTEN (SPIxCON1<5>) = 1 and
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SPIBEN (SPIxCON2<0>) = 1
MSTEN (SPIxCON1<5>) = 1)
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
MSb
MSb
SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
8-Level FIFO Buffer
Serial Transmit Buffer
Serial Receive Buffer
Shift Register
(SPIxBUF)
SPIx Buffer
(SPIxSR)
Shift Register
(SPIxBUF)
SPIx Buffer
(SPIxRXB)
(SPIxTXB)
(SPIxSR)
(2)
(2)
LSb
LSb
SDOx
SCKx
SDIx
SDOx
SDIx
SCKx
SSx
Preliminary
Serial Clock
Serial Clock
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
SDIx
SDOx
SCKx
SSx
SCKx
SDIx
SDOx
SSx
PROCESSOR 2 (SPI Enhanced Buffer Slave)
(1)
(1)
PROCESSOR 2 (SPI Slave)
MSb
Serial Transmit Buffer
Serial Receive Buffer
MSTEN (SPIxCON1<5>) = 0 and
SSEN (SPIxCON1<7>) = 1,
SPIBEN (SPIxCON2<0>) = 1
Shift Register
(SPIxBUF)
SPIx Buffer
(SPIxRXB)
MSb
(SPIxTXB)
(SPIxSR)
8-Level FIFO Buffer
Shift Register
(SPIxBUF)
SPIx Buffer
(SPIxSR)
(2)
© 2009 Microchip Technology Inc.
LSb
(2)
LSb
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