DSPIC30F3013-30I/SP Microchip Technology, DSPIC30F3013-30I/SP Datasheet - Page 33
DSPIC30F3013-30I/SP
Manufacturer Part Number
DSPIC30F3013-30I/SP
Description
IC DSPIC MCU/DSP 24K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3013-30I/SP
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301330ISP
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F3012-20ISO PDF datasheet #3
- DSPIC30F3012-20ISO PDF datasheet #4
- DSPIC30F3014-30IP PDF datasheet #5
- Current page: 33 of 244
- Download datasheet (7Mb)
3.0
3.1
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction EA, or data space EA, when pro-
gram space is mapped into data space, as defined by
Table 3-1. Note that the program space address is
incremented by two between successive program
words, in order to provide compatibility with data space
addressing.
TABLE 3-1:
FIGURE 3-1:
2004 Microchip Technology Inc.
Instruction Access
TBLRD/TBLWT
TBLRD/TBLWT
Program Space Visibility
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmer’s Reference Manual (DS70030).
Access Type
MEMORY ORGANIZATION
Program Address Space
PROGRAM SPACE ADDRESS CONSTRUCTION
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
Using
Program
Counter
Using
Program
Space
Visibility
Using
Table
Instruction
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
User
User
(TBLPAG<7> = 0)
Configuration
(TBLPAG<7> = 1)
User
Space
Select
User/
Configuration
1/0
0
0
Access
Space
PSVPAG Reg
TBLPAG Reg
8 bits
8 bits
Select
Preliminary
<23>
Program Counter
0
0
TBLPAG<7:0>
TBLPAG<7:0>
24-bit EA
23 bits
1
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the configuration bits. Otherwise, bit 23 is always
clear.
Note:
<22:16>
PSVPAG<7:0>
15 bits
16 bits
Program Space Address
EA
EA
The address map shown in Figure 3-5 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
PC<22:1>
<15>
Select
Byte
0
Data EA <15:0>
Data EA <15:0>
dsPIC30F
<14:1>
Data EA <14:0>
DS70082G-page 31
<0>
0
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