DSPIC30F3013-30I/SP Microchip Technology, DSPIC30F3013-30I/SP Datasheet - Page 77
DSPIC30F3013-30I/SP
Manufacturer Part Number
DSPIC30F3013-30I/SP
Description
IC DSPIC MCU/DSP 24K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3013-30I/SP
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301330ISP
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F3012-20ISO PDF datasheet #3
- DSPIC30F3012-20ISO PDF datasheet #4
- DSPIC30F3014-30IP PDF datasheet #5
- Current page: 77 of 244
- Download datasheet (7Mb)
9.5.1
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the period
register, and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC will con-
tinue to operate, provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
2004 Microchip Technology Inc.
RTC OSCILLATOR OPERATION
Preliminary
9.5.2
When an interrupt event occurs, the respective inter-
rupt flag, T1IF, is asserted and an interrupt will be gen-
erated, if enabled. The T1IF bit must be cleared in
software. The respective Timer interrupt flag, T1IF, is
located in the IFS0 status register in the Interrupt
Controller.
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The Timer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
RTC INTERRUPTS
dsPIC30F
DS70082G-page 75
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