DSPIC30F3010-30I/SO Microchip Technology, DSPIC30F3010-30I/SO Datasheet - Page 55
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DSPIC30F3010-30I/SO
Manufacturer Part Number
DSPIC30F3010-30I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3010-30I/SO
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301030ISO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3010-30I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.2
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
In addition to External Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
• Watchdog Time-out:
• Uninitialized W Register Trap:
• Illegal Instruction Trap:
• Brown-out Reset (BOR):
• Trap Lockout:
5.3
Traps can be considered as non-maskable, non-stable
interrupts, which adhere to a predefined priority as
shown in Figure 5-2. They are intended to provide the
user a means to correct erroneous operation during
debug and when operating within the application.
2004 Microchip Technology Inc.
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
A momentary dip in the power supply to the
device has been detected, which may result in
malfunction.
Occurrence of multiple Trap conditions simulta-
neously will cause a Reset.
Note:
Reset Sequence
Traps
RESET SOURCES
If the user does not intend to take correc-
tive action in the event of a trap error con-
dition, these vectors must be loaded with
the address of a default handler that sim-
ply contains the RESET instruction. If, on
the other hand, one of the vectors contain-
ing an invalid address is called, an
address error trap is generated.
Preliminary
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The Math Error trap executes under the following three
circumstances:
1.
2.
3.
4.
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
1.
2.
3.
4.
Note:
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
A misaligned data word access is attempted.
A data fetch from our unimplemented data mem-
ory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
TRAP SOURCES
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
dsPIC30F
DS70082G-page 53