PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet
PIC18F2420-I/ML
Specifications of PIC18F2420-I/ML
Available stocks
Related parts for PIC18F2420-I/ML
PIC18F2420-I/ML Summary of contents
Page 1
... Any Data Sheet Clarification issues related to the PIC18F2420/2520/4420/4520 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. All the problems listed here will be addressed in future revisions of the PIC18F2420/2520/4420/4520 silicon. ...
Page 2
... PIC18F2420/2520/4420/4520 2. Module: MSSP When the MSSP is configured for SPI Master mode, the SDO pin cannot be disabled by setting the TRISC<5> bit. The SDO pin always outputs the content of SSPBUF regardless of the state of the TRIS bit. In Slave mode with Slave Select enabled, SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the SDO pin can be disabled by placing a logic high level on the SS pin (RA5) ...
Page 3
... None. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 9. Module: ECCP and CCP The CCP1 and CCP2 configured for PWM mode, with 1:1 Timer2 prescaler and duty cycle set to the period minus 1, may result in the PWM output(s) remaining at a logic low level ...
Page 4
... PIC18F2420/2520/4420/4520 12. Module: ECCP The PWM pin(s) may change state if a breakpoint is encountered during emulation and an auto- shutdown event occurs via FLT0. This affects the ® MPLAB ICD 2 debugger and the ICE 2000 and ICE 4000 emulators. Work around During emulation, use the comparator for auto- shutdown ...
Page 5
... BORV1:BORV0 = 11 N/A 2.05 N/A Work around Use the next higher BOD voltage setting to ensure a low V is detected above 2.0V. DD Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 + and V - REF REF PIC18LFX42X/X52X (INDUSTRIAL) Min Typ Max — ...
Page 6
... PIC18F2420/2520/4420/4520 19. Module: EUSART When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTA register is set), the second byte may be corrupted written into TXREG immediately after the TMRT bit is set. Work around Execute a software delay, at least one-half the transmission’s bit time, after TMRT is set and prior to writing subsequent bytes into TXREG ...
Page 7
... ISR code here : RETFIE FAST © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Work around 1. Assembly Language Programming any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt. Instead, save/restore WREG, BSR and STATUS via software per Example 9-1 in the Device Data Sheet ...
Page 8
... PIC18F2420/2520/4420/4520 2. C Language Programming: The exact work around depends on the compiler in use. Please refer to your C compiler documentation for details. ® If using the Microchip MPLAB define both high and low priority interrupt han- dler functions as “low priority” by using the directive. pragma interruptlow ...
Page 9
... SSPBUF and clear SSPOV. Discard the data from SSPBUF. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 28. Module: MSSP Master mode, the BRG value of ‘0’ may not work correctly. ...
Page 10
... PIC18F2420/2520/4420/4520 31. Module: MSSP In SPI mode, the Buffer Full flag (BF bit in the SSPSTAT register), the Write Collision Detect bit (WCOL bit in SSPCON1) and the Receive Overflow Indicator bit (SSPOV in SSPCON1) are not reset upon disabling the SPI module (by clearing the SSPEN bit in the SSPCON1 register). ...
Page 11
... WUE bit is automatically cleared. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 37. Module: MSSP The MSSP configured in SPI Slave mode will generate a write collision if SSPBUF is updated and the previous SSPBUF contents have not been ...
Page 12
... PIC18F2420/2520/4420/4520 39. Module: MSSP In SPI mode, the SDO output may change after the inactive clock edge of the bit ‘0’ output. This may affect some SPI components that read data over 300 ns after the inactive edge of SCK. Work around None Date Codes that pertain to this issue: All engineering and production devices ...
Page 13
... Change the 7-bit slave address in SSPADD to an address in the range of 0x08 to 0x77. • Use Revision B silicon This version of silicon removes this issue’s addressing restrictions. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Slave mode DS80209H-page 13 ...
Page 14
... PIC18F2420/2520/4420/4520 REVISION HISTORY Rev A Document (9/2004) First revision of this document which includes silicon issues 1-6 (ECCP), 7-11 (MSSP), 12 (ECCP and CCP), 13 (A/D), 14-15 (Timer1/Timer3) and 16 (BOD/HLVD). Rev B Document (11/2004) Changes made to silicon issue 7 (MSSP), 9 (MSSP) and 10 (MSSP). Added silicon issue 17 (EUSART), 18 (Interrupts), 19 (ECCP) and 20 (Timer1/Timer3) ...
Page 15
... PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 16
... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...