PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet - Page 9

• Manufacturer Part Number: PIC18F2420-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2420-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24. Module: EUSART
25. Module: EUSART
26. Module: EUSART
27. Module: MSSP
© 2008 Microchip Technology Inc.
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In Synchronous mode (SYNC = 1) with clock
polarity high (SCKP = 1), the EUSART transmits a
shorter than expected clock on the CK pin for bit 0.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In Synchronous mode, EUSART baud rates using
SPBRG values of ‘0’ and ‘1’ may not function
correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Date Codes that pertain to this issue:
All engineering and production devices.
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit and load
SSPBUF. The second occurrence will set the
SSPOV bit and the I
to I
In both occurrences, no NACK bit is sent; the
SSPIF bit is not set and no interrupt will occur.
Work around
The I
independently of SSPIF interrupts. If BF is set and
SSPIF is clear, retest BF to ensure that an interrupt
was not just processed. If BF is still set, the slave
should read SSPBUF and clear SSPOV. Discard
the data from SSPBUF.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C activity.
2
2
C slave must periodically poll the BF flag
C™ system with multiple slave nodes, an
2
C slave will stop responding
PIC18F2420/2520/4420/4520
28. Module: MSSP
29. Module: MSSP
30. Module: MSSP
In I
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPADD ≥ 1.
Date Codes that pertain to this issue:
All engineering and production devices.
In I
ware to begin data reception and cleared by the
peripheral after a byte is received. After a byte is
received, the device may take up to 80 T
RCEN and 800 T
and MPLAB ICE emulators.
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions is
typically long enough for the RCEN bit to clear. For
multiple byte receptions, the software must wait
until the bit is cleared by the peripheral before the
next byte can be received.
Date Codes that pertain to this issue:
All engineering and production devices.
Setting the SEN bit initiates a Start sequence on
the bus, after which, the SEN bit is cleared auto-
matically by hardware. If the SEN bit is set again
(without an address byte being transmitted), a
Start sequence will not commence and the SEN bit
will not be cleared. This condition causes the bus
to remain in an active state. The system is Idle
when ACKEN, RCEN, PEN, RSEN and SEN are
clear.
Work around
Set the PEN or RSEN bit to transmit a Stop or
Repeated Start sequence, although the SEN bit
may still be set, indicating the bus is active. After
the sequence has completed, the PEN, RSEN and
SEN bit will be clear, indicating the bus is Idle.
Clearing and setting the SSPEN bit will also reset
the I
SEN status bits.
Date Codes that pertain to this issue:
All engineering and production devices.
2
2
C Master mode, the BRG value of ‘0’ may not
C Master mode, the RCEN bit is set by soft-
2
C peripheral and clear the PEN, RSEN and
CY
when using MPLAB
DS80209H-page 9
CY
®
to clear
ICD 2