PIC18F2520-I/SO Microchip Technology, PIC18F2520-I/SO Datasheet - Page 277

• Manufacturer Part Number: PIC18F2520-I/SO
• Description: IC MCU FLASH 16KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2520-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILMCP3909RD-3PH1 - REF DESIGN MCP3909 3PH ENGY MTR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
ANDWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .AND. (f) → dest
N, Z
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ANDWF
Read
0001
Q2
17h
C2h
02h
C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
ffff
destination
Write to
PIC18F2420/2520/4420/4520
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Carry
If Carry
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
BC
-128 ≤ n ≤ 127
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
None
If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
0010
BC
operation
Process
Process
Data
Data
Q3
No
Q3
DS39631E-page 275
5
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn