PIC24HJ64GP502-I/MM Microchip Technology, PIC24HJ64GP502-I/MM Datasheet - Page 7

• Manufacturer Part Number: PIC24HJ64GP502-I/MM
• Description: IC PIC MCU FLASH 64K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP502-I/MM

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel / 12 bit, 10 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 4KB
• Cpu Speed: 40MIPS
• No. Of Timers: 7
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16. Module: ECAN
17. Module: ECAN
© 2010 Microchip Technology Inc.
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN Event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
The ECAN module may not store received data in
the correct location. When this occurs, the receive
buffers will become corrupted. In addition, it is also
possible for the transmit buffers to become
corrupted. This issue is more likely to occur as the
CAN bus speed approaches 1 Mbps.
Work around
Do not use the DMA with ECAN in Peripheral
Indirect mode. Use the DMA in Register Indirect
mode, Continuous mode enabled and Ping Pong
mode disabled. The receive DMA channel count
should be set to 8 words. The transmit DMA
channel count should be set for the actual
message size (maximum of 7 words for Extended
CAN messages and 6 words for Standard CAN
Messages). To simplify application error handling
while using this mode, only one TX buffer should
be used. While message filtering is not affected,
messages will not be stored at distinct RX buffers.
Instead all messages are stored contiguously in
memory. The start of this memory is pointed to by
the receive DMA channel. The application must
still clear RXFUL flags and other interrupt flags.
The application must manage the RX buffer
memory.
Affected Silicon Revisions
A1
A1
X
X
A2
A2
X
X
repetitive
A3
A3
X
X
A4
A4
Interrupt
X
Service
Routine
18. Module: CPU
19. Module: SPI
The EXCH instruction does not execute correctly.
Work around
If
recommended work around is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
Options > Projects > MPLAB C30 > Use Alternate
Settings).
Affected Silicon Revisions
Writing to the SPIxBUF register as soon as the
TBF bit is cleared will cause the SPI module to
ignore the written data applications which use SPI
with DMA will not be affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI clock before writing to the
SPIxBUF register.
Alternatively, do one of the following:
1. Poll the RBF bit and wait for it to get set before
2. Poll the SPI Interrupt flag and wait for it to get
3. Use an SPI Interrupt Service Routine.
4. Use DMA.
Affected Silicon Revisions
A1
A1
X
X
writing to the SPIxBUF register.
set before writing to the SPIxBUF register.
writing
A2
A2
X
X
source
A3
A3
X
X
A4
A4
X
X
code
in
DS80441F-page 7
assembly,
the