PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet - Page 245

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: IC PIC MCU FLASH 12KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2455-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 20-4:
FIGURE 20-5:
TABLE 20-5:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1:
Note:
(Interrupt Reg. Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
Name
Reg. Empty Flag)
(Transmit Shift
Write to TXREG
(Transmit Shift
BRG Output
(Shift Clock)
BRG Output
(Shift Clock)
TRMT bit
This timing diagram shows two consecutive transmissions.
TXIF bit
TRMT bit
Reserved in 28-pin devices; always maintain these bits clear.
TXIF bit
(pin)
TX
(pin)
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
SPPIE
SPPIP
SPPIF
TX
SPEN
CSRC
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
1 T
(1)
(1)
(1)
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
CY
Transmit Shift Reg.
Word 1
Transmit Shift Reg
Word 1
Word 1
Word 1
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
1 T
CY
Start bit
Start bit
Word 2
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
1 T
PIC18F2455/2550/4455/4550
CY
bit 0
bit 0
Preliminary
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
bit 1
Word 1
bit 1
Word 1
ADDEN
SENDB
BRG16
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 7/8
bit 7/8
Word 2
Transmit Shift Reg.
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
Stop bit
TRMT
WUE
Bit 1
Stop bit
Start bit
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
DS39632B-page 243
TX9D
RBIF
Bit 0
Word 2
on page
bit 0
Values
Reset
51
54
54
54
53
53
53
53
53
53