PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet - Page 414

IC PIC MCU FLASH 12KX16 28DIP

PIC18F2455-I/SP

Manufacturer Part Number
PIC18F2455-I/SP
Description
IC PIC MCU FLASH 12KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2455-I/SP

Program Memory Type
FLASH
Program Memory Size
24KB (12K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI/I2C/EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2455-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2455/2550/4455/4550
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 322
H
Hardware Multiplier ............................................................ 95
High/Low-Voltage Detect ................................................. 273
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 111
I
DS39632B-page 412
2
C Mode (MSSP)
Table Pointer Boundaries .......................................... 82
Table Reads and Table Writes .................................. 79
Unexpected Termination of Write .............................. 87
Write Sequence ......................................................... 85
Write Verify ................................................................ 87
Writing To ................................................................... 85
Introduction ................................................................ 95
Operation ................................................................... 95
Performance Comparison .......................................... 95
Applications .............................................................. 276
Associated Registers ............................................... 277
Characteristics ......................................................... 373
Current Consumption ............................................... 275
Effects of a Reset ..................................................... 277
Operation ................................................................. 274
Setup ........................................................................ 275
Start-up Time ........................................................... 275
Typical Application ................................................... 276
Acknowledge Sequence Timing ............................... 226
Associated Registers ............................................... 232
Baud Rate Generator ............................................... 219
Bus Collision
Clock Arbitration ....................................................... 220
Clock Stretching ....................................................... 212
Clock Synchronization and the CKP Bit ................... 213
Effect of a Reset ...................................................... 227
General Call Address Support ................................. 216
I
Master Mode ............................................................ 217
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 227
Operation ................................................................. 206
Read/Write Bit Information (R/W Bit) ............... 206, 207
Registers .................................................................. 202
Serial Clock (RB1/AN10/INT1/SCK/SCL) ................ 207
2
C Clock Rate w/BRG ............................................. 219
During Sleep .................................................... 277
During a Repeated Start Condition .................. 230
During a Stop Condition ................................... 231
10-Bit Slave Receive Mode (SEN = 1) ............. 212
10-Bit Slave Transmit Mode ............................. 212
7-Bit Slave Receive Mode (SEN = 1) ............... 212
7-Bit Slave Transmit Mode ............................... 212
Operation ......................................................... 218
Reception ......................................................... 223
Repeated Start Condition Timing ..................... 222
Start Condition Timing ..................................... 221
Transmission .................................................... 223
Transmit Sequence .......................................... 218
and Arbitration .................................................. 227
Preliminary
ID Locations ............................................................. 279, 299
Idle Modes ......................................................................... 39
INCF ................................................................................ 322
INCFSZ ............................................................................ 323
In-Circuit Debugger .......................................................... 299
In-Circuit Serial Programming (ICSP) ...................... 279, 299
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ................................. 75, 77, 348
Indirect Addressing ............................................................ 73
INFSNZ ............................................................................ 323
Initialization Conditions for all Registers ...................... 51–55
Instruction Cycle ................................................................ 61
Instruction Format ............................................................ 303
Instruction Set .................................................................. 301
Slave Mode .............................................................. 206
Sleep Operation ....................................................... 227
Stop Condition Timing ............................................. 226
and Standard PIC18 Instructions ............................. 348
Clocking Scheme ....................................................... 61
Flow/Pipelining ........................................................... 61
ADDLW .................................................................... 307
ADDWF .................................................................... 307
ADDWF (Indexed Literal Offset mode) .................... 349
ADDWFC ................................................................. 308
ANDLW .................................................................... 308
ANDWF .................................................................... 309
BC ............................................................................ 309
BCF ......................................................................... 310
BN ............................................................................ 310
BNC ......................................................................... 311
BNN ......................................................................... 311
BNOV ...................................................................... 312
BNZ ......................................................................... 312
BOV ......................................................................... 315
BRA ......................................................................... 313
BSF .......................................................................... 313
BSF (Indexed Literal Offset mode) .......................... 349
BTFSC ..................................................................... 314
BTFSS ..................................................................... 314
BTG ......................................................................... 315
BZ ............................................................................ 316
CALL ........................................................................ 316
CLRF ....................................................................... 317
CLRWDT ................................................................. 317
COMF ...................................................................... 318
CPFSEQ .................................................................. 318
CPFSGT .................................................................. 319
CPFSLT ................................................................... 319
DAW ........................................................................ 320
DCFSNZ .................................................................. 321
DECF ....................................................................... 320
DECFSZ .................................................................. 321
GOTO ...................................................................... 322
INCF ........................................................................ 322
INCFSZ .................................................................... 323
INFSNZ .................................................................... 323
IORLW ..................................................................... 324
IORWF ..................................................................... 324
LFSR ....................................................................... 325
Addressing ....................................................... 206
Reception ........................................................ 207
Transmission ................................................... 207
 2004 Microchip Technology Inc.

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