PIC18F4520-I/P Microchip Technology, PIC18F4520-I/P Datasheet - Page 166
![IC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4520-I/P
Manufacturer Part Number
PIC18F4520-I/P
Description
IC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2420-IML.pdf
(412 pages)
4.PIC18F2420-IML.pdf
(16 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(6 pages)
7.PIC18F2420-IML.pdf
(8 pages)
8.PIC18F2420-IML.pdf
(4 pages)
9.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F4520-I/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
ST
Quantity:
104
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Quantity:
20 000
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Part Number:
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PIC18F2420/2520/4420/4520
17.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
EXAMPLE 17-1:
DS39631A-page 164
LOOP
output time)
SCK)
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
OPERATION
SSPSTAT, BF
LOOP
SSPBUF, W
RXDATA
TXDATA, W
SSPBUF
LOADING THE SSPBUF (SSPSR) REGISTER
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
Preliminary
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 17-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
2004 Microchip Technology Inc.