PIC18F4520-I/P Microchip Technology, PIC18F4520-I/P Datasheet - Page 289
![IC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4520-I/P
Manufacturer Part Number
PIC18F4520-I/P
Description
IC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2420-IML.pdf
(412 pages)
4.PIC18F2420-IML.pdf
(16 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(6 pages)
7.PIC18F2420-IML.pdf
(8 pages)
8.PIC18F2420-IML.pdf
(4 pages)
9.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F4520-I/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4520-I/P
Manufacturer:
ST
Quantity:
104
Part Number:
PIC18F4520-I/P
Manufacturer:
MICROCH
Quantity:
20 000
Company:
Part Number:
PIC18F4520-I/PT
Manufacturer:
TI
Quantity:
14 300
Company:
Part Number:
PIC18F4520-I/PT
Manufacturer:
Microchip Technology
Quantity:
33 055
Company:
Part Number:
PIC18F4520-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4520-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
If CNT
Q1
No
Q1
No
No
Q1
PC =
PC =
=
=
=
register ‘f’
operation
operation
operation
Decrement f, skip if 0
DECFSZ f {,d {,a}}
0
d
a
(f) – 1
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
Q2
Q2
No
No
No
Q2
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
f
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
11da
GOTO
DECFSZ
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
95 (5Fh). See
ffff
CNT, 1, 1
LOOP
destination
operation
operation
operation
PIC18F2420/2520/4420/4520
Write to
Q4
Q4
Q4
No
No
No
ffff
Preliminary
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
No
Q1
No
No
PC
PC
register ‘f’
operation
operation
operation
Decrement f, skip if not 0
DCFSNZ
0
d
a
(f) – 1
skip if result
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
Q2
Q2
Q2
No
No
No
f
[0,1]
[0,1]
255
=
=
=
=
=
3 cycles if skip and followed
by a 2-word instruction.
dest,
DCFSNZ
:
:
f {,d {,a}}
11da
operation
operation
operation
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
0
Process
Data
Q3
Q3
No
Q3
No
No
DS39631A-page 287
95 (5Fh). See
ffff
TEMP, 1, 0
destination
operation
operation
operation
Write to
Q4
Q4
No
Q4
No
No
ffff