DSPIC30F4012-30I/SO Microchip Technology, DSPIC30F4012-30I/SO Datasheet - Page 95

• Manufacturer Part Number: DSPIC30F4012-30I/SO
• Description: IC DSPIC MCU/DSP 48K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 20
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401230ISO

TABLE 14-1:
QEICON
DFLTCON 0124
POSCNT
MAXCNT
ADPCFG
Legend:
Note
Name
SFR
1:
Addr.
0122 CNTERR
0126
0128
02A8
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Bit 15
QEI REGISTER MAP
—
—
Bit 14
—
—
—
QEISIDL
Bit 13
—
—
Bit 12
INDX
—
—
(1)
Bit 11
UPDN
—
—
QEIM2
Bit 10
IMV1
—
QEIM1 QEIM0 SWPAB
IMV0
Bit 9
—
PCFG8 PCFG7 PCFG6 PCFG5
CEID
Bit 8
Position Counter<15:0>
Maximun Count<15:0>
QEOUT QECK2 QECK1
Bit 7
Bit 6
—
TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 0000 0000
Bit 5
QECK0
PCFG4
Bit 4
PCFG3
Bit 3
—
PCFG2
Bit 2
—
PCFG1
Bit 1
—
PCFG0
Bit 0
—
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
Reset State