PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet

IC PIC MCU FLASH 16KX16 28DIP

PIC18F2550-I/SP

Manufacturer Part Number
PIC18F2550-I/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2550-I/SP

Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2550-I/SP
Manufacturer:
MICROCHIP
Quantity:
2 100
The PIC18F2455/2550/4455/4550 family devices that
you have received conform functionally to the current
Device Data Sheet (DS39632D), except for the anoma-
lies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18F2455/2550/4455/4550
silicon.
Data Sheet clarifications and corrections start on page 18,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
© 2009 Microchip Technology Inc.
PIC18F2455
PIC18F2550
PIC18F4455
PIC18F4550
Note 1:
Note:
Part Number
2:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the “PIC18F2XXX/4XXX Family Flash Microcontroller Programming Specification” (DS39622) for
detailed information on Device and Revision IDs for your specific device.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon revision
(B7).
SILICON DEVREV VALUES
Silicon Errata and Data Sheet Clarification
Device ID
PIC18F2455/2550/4455/4550 Family
126Xh
124Xh
122Xh
120Xh
®
IDE and Microchip’s
(1)
PIC18F2455/2550/4455/4550
A3
2h
Revision ID for Silicon Revision
B4
4h
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
2.
3.
4.
The DEVREV values for the various PIC18F2455/2550/
4455/4550 silicon revisions are shown in Table 1.
Note:
Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
Select
(Debugger>Select Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number and Device
Revision ID value appear in the Output window.
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
B5
5h
the
MPLAB
B6
6h
(2)
hardware
DS80478A-page 1
B7
7h
tool

Related parts for PIC18F2550-I/SP

PIC18F2550-I/SP Summary of contents

Page 1

... TABLE 1: SILICON DEVREV VALUES (1) Part Number Device ID PIC18F2455 126Xh PIC18F2550 124Xh PIC18F4455 122Xh PIC18F4550 120Xh Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. ...

Page 2

... Asynch Reset can alter RAM Dead-band delay incorrect SPI master, write collision for F /64 and OSC Timer2/2 2 Unaddressed I C slave node may respond Auto-baud sometimes does not work not meeting data sheet at 511/512 IL DL (1) Affected Revisions © 2009 Microchip Technology Inc. ...

Page 3

... I C Master 40. EUSART Interrupts 41. Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Issue Summary Clearing SBOREN can cause BOR baud rate not meeting formula SPI slave not meeting timing parameter 70 ...

Page 4

... Work around Avoid writing SSPBUF until the data transfer is complete, indicated by the setting of the SSPIF bit (PIR1<3>). To ensure any potential transfer in progress is not corrupted, verify (SSPCON1<7>) is clear after writing SSPBUF. Affected Silicon Revisions that the WCOL bit © 2009 Microchip Technology Inc. ...

Page 5

... POP ; clears return address of Foo call : ; insert high priority ISR code here : RETFIEFAST © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Assembly Language Programming Either of two work arounds can be used: • If any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt ...

Page 6

... This EXAMPLE 3: #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr B7 void high_isr (void) { ... } in Example 2 INTERRUPT WORK AROUND – OPTIMIZED C18 © 2009 Microchip Technology Inc. ...

Page 7

... ECCPASE bit (ECCP1AS<7>). Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 7. Module: ECCP When operating either Timer1 or Timer3 as a counter with a prescale value other than 1:1 and operating the ECCP in Compare mode with the Special CCP1M<3:0> = 1011), the Special Event Trigger ...

Page 8

... The PKTDIS bit is set when a USB control transfer setup packet is received. Clear this bit as soon as possible, particularly before turning over any IN endpoint ownership to the SIE. Affected Silicon Revisions and V - REF REF Conditions and V - REF REF REF and V REF © 2009 Microchip Technology Inc. ...

Page 9

... Work around None. Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 14. Module: USB The Ping-Pong Buffer mode in which the ping-pong buffers are enabled for Endpoints (UCFG (PPB<1:0) = 11) is not supported. Work around Use other Ping-Pong Buffer modes. Affected Silicon Revisions ...

Page 10

... BTFSS BRA A second option is to poll the Master Synchronous Serial Port Interrupt Flag bit, SSPIF (PIR1<3>). This bit can be polled and will set when the transfer is complete Affected Silicon Revisions SSPSTAT WORK AROUND SSPSTAT, W WREG, BF loop_MSB © 2009 Microchip Technology Inc. ...

Page 11

... TXREG. Do not load the TXREG when timer is about to overflow. Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 20. Module: EUSART In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON<6>) is set. Work around Write to TX9D only when a reception is not in progress (RCIDL = 1) ...

Page 12

... PWM duty cycle. This can occur when these additional criteria are also met: • A non-zero dead-band delay is specified (PDC<6:0> > 0) • The duty cycle has a value of 0 through ≥ 1) Work around None. Affected Silicon Revisions described in Note © 2009 Microchip Technology Inc. ...

Page 13

... I C event to maintain normal operation. Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 28. Module: EUSART /64 or The EUSART auto-baud feature may periodically OSC measure the incoming baud rate incorrectly. The rate of incorrect baud-rate measurements will depend on the frequency of the incoming synchronization byte and the system clock frequency ...

Page 14

... SCK edge or loading SSPBUF, the peripheral will function correctly. Also, if SSPBUF is written prior to the SS pin going low, the peripheral will function correctly. B7 Characteristic Work around None. Affected Silicon Revisions the falling edge before the CY Min Max Units Conditions 3 T — © 2009 Microchip Technology Inc. ...

Page 15

... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 35. Module: Resets (BOR) Certain operating conditions can move the effec- tive Brown-out Reset (BOR) threshold outside of the range specified in the electrical characteristics of the Device Data Sheet (parameter D005). The BOR threshold has been observed to increase with some table read operations ...

Page 16

... Example 7 (Assembly language) and Example 8 (C language). Affected Silicon Revisions A3 // Reads from SSPBUF, ensures BF bit is clear before // sending the next byte. // Wait until the transmission is complete. // The data received should be valid © 2009 Microchip Technology Inc. ...

Page 17

... Tcy delay nop ;1 Tcy delay (two total) ;CPU may now execute 2 cycle instructions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 40. Module: MSSP (I When in I clock stretching, the first clock pulse after the slave releases the SCL line may be narrower than the configured clock width ...

Page 18

... If TMR1 update can be completed before clock pulse goes low ; Start ISR here ; Preload for 1 sec overflow ; Clear interrupt flag ; Increment seconds ; 60 seconds elapsed? ; No, done ; Clear seconds ; Increment minutes ; 60 minutes elapsed? ; No, done ; clear minutes ; Increment hours ; 24 hours elapsed? ; No, done ; Reset hours ; Done © 2009 Microchip Technology Inc. ...

Page 19

... The sentence originally stated, “V greater than V at all times, even with the USB regulator disabled.” © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 4. Module: Master Synchronous Serial Port In Section 19.3.5 “Master Mode,” the second paragraph of the second column is corrected to read, “This allows a maximum data rate (at 48 MHz) of 12.00 Mbps.” ...

Page 20

... Min Max Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T (†) Min Typ Max /RE3 pin 9.00 — 13.25 ≤ +85°C for industrial A Units Conditions ≤ +85°C for industrial A Units Conditions V (Note 2) © 2009 Microchip Technology Inc. ...

Page 21

... TABLE 28-5: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS (PARTIAL PRESENTATION) Operating Conditions: -40°C < T < +85°C (unless otherwise stated). A Param Sym Characteristics No. D323 V Regulator Output Voltage USBANA © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Min Typ Max Units 3.0 — 3.6 Comments ≥ 4. ...

Page 22

... PR2 match condition at the moment that the firmware wrote to SSPBUF. To avoid the unpredictable MSb bit width, initial- ize the TMR2 register to a known value when writing to SSPBUF. An example procedure, which provides predictable bit widths (only needed in the Timer2/2 mode), is given in Example 10. © 2009 Microchip Technology Inc. ...

Page 23

... Revision B4 Silicon Errata” • DS80322, “PIC18F2455/2550/4455/4550 Revision B5 Silicon Errata” • DS80335, “PIC18F2455/2550/4455/4550 Revision B6 Silicon Errata” • DS80388, “PIC18F2455/2550/4455/4550 Revision B7 Silicon Errata” • DS80278, “PIC18F2455/2550/4455/4550 Data Sheet Errata” © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 C Master) and DS80478A-page 23 ...

Page 24

... PIC18F2455/2550/4455/4550 NOTES: DS80478A-page 24 © 2009 Microchip Technology Inc. ...

Page 25

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 26

... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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