PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet
PIC18F2550-I/SP
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... PIC18F2455/2550/4455/4550 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers © 2009 Microchip Technology Inc. Data Sheet with nanoWatt Technology DS39632E ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops Program Memory Device Flash # Single-Word SRAM (bytes) Instructions (bytes) PIC18F2455 24K 12288 2048 PIC18F2550 32K 16384 2048 PIC18F4455 24K 12288 2048 PIC18F4550 32K 16384 2048 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Peripheral Highlights: • ...
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... USB REF USB RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 (1) RB3/AN9/CCP2 /VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA RC7/RX/DT/SDO RC6/TX/CK RC5/D+/VP RC4/D-/VM RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0/CSSPP (1) RB3/AN9/CCP2 /VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA RD7/SPP7/P1D RD6/SPP6/P1C RD5/SPP5/P1B RD4/SPP4 RC7/RX/DT/SDO RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3/SPP3 RD2/SPP2 © 2009 Microchip Technology Inc. ...
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... RB0/AN12/INT0/FLT0/SDI/SDA RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features available in select circumstances. See Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for more information. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 33 NC/ICRST 1 32 RC0/T1OSO/T13CKI 2 31 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 421 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 421 Index .................................................................................................................................................................................................. 423 The Microchip Web Site ..................................................................................................................................................................... 433 Customer Change Notification Service .............................................................................................................................................. 433 Customer Support .............................................................................................................................................................................. 433 Reader Response .............................................................................................................................................................................. 434 PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 435 DS39632E-page 4 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 DS39632E-page 5 ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 6 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2455 • PIC18LF2455 • PIC18F2550 • PIC18LF2550 • PIC18F4455 • PIC18LF4455 • PIC18F4550 • PIC18LF4550 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – ...
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... Like all Microchip PIC18 devices, members of the PIC18F2455/2550/4455/4550 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2550), accommodate an operating V range of 4.2V to 5.5V. DD Low-voltage parts, designated by “LF” (such as PIC18LF2550), function over an extended ...
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... Stack Underflow (PWRT, OST), MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 PIC18F2455 PIC18F2550 DC – 48 MHz DC – 48 MHz 24576 32768 12288 16384 2048 2048 256 256 19 19 Ports (E) ...
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... EUSART USB 10-Bit PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO/RA6 PORTB RB0/AN12/INT0/FLT0/SDI/SDA RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO (3) RB3/AN9/CCP2 /VPO RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (3) RC1/T1OSI/CCP2 /UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT/SDO PORTE (1) MCLR/V /RE3 PP © 2009 Microchip Technology Inc. ...
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... These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Bus<8> Data Latch ...
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... Crystal Oscillator mode. O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description 2 C mode. © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer ...
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... TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description 2 C mode. © 2009 Microchip Technology Inc. ...
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... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer ...
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... I/O TTL Streaming Parallel Port data. O — Enhanced CCP1 PWM output, channel C. 5 I/O ST Digital I/O. I/O TTL Streaming Parallel Port data. O — Enhanced CCP1 PWM output, channel D. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 22 © 2009 Microchip Technology Inc. ...
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... The OSCTUNE register (Register 2-1) is used to trim the INTRC frequency source, as well as select the low-frequency clock source that drives several special features. Its use is described in Section 2.2.5.2 “OSCTUNE Register”. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 2.2 Oscillator Types PIC18F2455/2550/4455/4550 devices can be operated in twelve distinct oscillator modes ...
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... OSCTUNE<7> USB Clock Source FSEN 1 USB Peripheral ÷ CPU Primary IDLEN Clock Peripherals T1OSC Clock Control OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2009 Microchip Technology Inc. ...
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... Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 series resistor (R ) may be required for AT S strip cut crystals varies with the oscillator mode chosen. F © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 2-1: Typical Capacitor Values Used: Mode XT HS 16.0 MHz Capacitor values are for design guidance only. ...
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... EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC AND ECPLL CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO AND ECPIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) © 2009 Microchip Technology Inc. ...
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... F OUT Prescaler Loop Filter VCO ÷24 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 2.2.5 INTERNAL OSCILLATOR BLOCK The PIC18F2455/2550/4455/4550 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. If the USB peripheral is not used, the internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins ...
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... INTRC and vice versa. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared or tempera- DD R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Finally, a CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... HSPLL, ECPLL, ECPIO ÷3 (01) ÷4 (10) ÷6 (11) Microcontroller Clock Frequency 48 MHz 24 MHz 16 MHz 12 MHz 48 MHz 24 MHz 16 MHz 12 MHz 48 MHz 32 MHz 24 MHz 16 MHz 40 MHz 20 MHz 13.33 MHz 10 MHz 48 MHz 32 MHz 24 MHz 16 MHz 24 MHz 12 MHz 8 MHz 6 MHz 48 MHz 32 MHz 24 MHz 16 MHz © 2009 Microchip Technology Inc. ...
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... Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Clock Mode MCU Clock Division (FOSC3:FOSC0) ...
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... It is recommended that the Timer1 oscillator be operating and stable prior to switching the clock source; other- wise, a very long delay may occur while the Timer1 oscillator starts. Oscillator Frequency Select bits, © 2009 Microchip Technology Inc. ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. ...
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... OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level consumption are listed in (parameter 38, CSD OSC2 Pin © 2009 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high-accuracy clock source. © 2009 Microchip Technology Inc ...
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... OST OSC PLL 2: Clock transition typically occurs within 2-4 T © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled © 2009 Microchip Technology Inc. ...
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... INTOSC Multiplexer OSC1 T OST PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 OST OSC PLL 2: Clock transition typically occurs within 2-4 T © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 n-1 n (1) Clock Transition OSC (1) PLL ( n-1 n (2) ...
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... RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits PLL ( OSTS bit Set CSD © 2009 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS1:SCS0 to ‘ ...
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... CSD mode (see Section 3.2 “Run © 2009 Microchip Technology Inc. ...
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... Oscillator Start-up Timer period (parameter 32, Table 28-12). t OST (parameter F12, Table 28-9 also designated Execution continues during T © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC and any internal oscillator modes) ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 44 © 2009 Microchip Technology Inc. ...
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... PWRT (1) INTRC 11-Bit Ripple Counter Note 1: This is the low-frequency INTRC source from the internal oscillator block. 2: See Table 4-2 for time-out situations. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39632E-page 46 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 4- ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. © 2009 Microchip Technology Inc. ...
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... INTHS, INTXT 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39632E-page PWRT T OST T PWRT T OST T PWRT T OST © 2009 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the Power-up Timer. T PLL © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 , V RISE > PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter POR BOR STKFUL 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ( STKPTR Register STKUNF © 2009 Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 58 © 2009 Microchip Technology Inc. ...
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... NOP instruction). The PIC18F2455 and PIC18F4455 each have 24 Kbytes of Flash memory and can store up to 12,288 single-word instructions. The PIC18F2550 and PIC18F4550 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack<20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. ...
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... Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...
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... Additional information on USB RAM and buffer operation is provided in Section 17.0 “Universal Serial Bus (USB)”. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 5.3.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Memory 000h ...
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... UEIE LATB F6Ah UEIR LATA F69h UIE (2) — F68h UIR (2) — F67h UFRMH (2) — F66h UFRML (2) (3) — F65h SPPCON (3) PORTE F64h SPPEPS (3) (3) PORTD F63h SPPCFG (3) PORTC F62h SPPDATA (2) PORTB F61h — (2) PORTA F60h — © 2009 Microchip Technology Inc. ...
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... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> C™ Slave mode only. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 4 Bit 3 Bit 2 — Top-of-Stack Upper Byte (TOS<20:16>) — ...
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... TMR3CS TMR3ON 55, 139 0000 0000 55, 247 0000 0000 55, 247 0000 0000 55, 256 0000 0000 55, 253 0000 0000 TRMT TX9D 0000 0010 55, 244 OERR RX9D 55, 245 0000 000x © 2009 Microchip Technology Inc. ...
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... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> C™ Slave mode only. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 4 Bit 3 Bit 2 — FREE ...
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... URSTIE 57, 183 -000 0000 UERRIF URSTIF 57, 181 -000 0000 FRM9 FRM8 57, 173 ---- -xxx FRM1 FRM0 xxxx xxxx 57, 173 SPPOWN SPPEN 57, 191 ---- --00 ADDR1 ADDR0 57, 195 00-0 0000 WS1 WS0 57, 192 0000 0000 DATA1 DATA0 57, 196 0000 0000 © 2009 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 It is recommended that only BCF, BSF, SWAPF, MOVFF ...
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... Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. ...
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... ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...
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... Indirect Addressing. Similarly, operations by Indirect Addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. © 2009 Microchip Technology Inc. ...
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... Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When using the extended instruction set, this addressing mode requires the following: • ...
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... FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 80 © 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-x R/W-0 ...
Page 86
... Figure 6-3 describes the relevant boundaries of the TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ – TBLPTR<21:0> TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 88
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
Page 89
... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...
Page 90
... TBLWT holding register. ; loop until buffers are full © 2009 Microchip Technology Inc. ...
Page 91
... USBIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 92
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 90 © 2009 Microchip Technology Inc. ...
Page 93
... EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory ...
Page 94
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39632E-page 92 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times except when updating the EEPROM ...
Page 96
... Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts © 2009 Microchip Technology Inc. ...
Page 97
... EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE ...
Page 98
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 96 © 2009 Microchip Technology Inc. ...
Page 99
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
Page 100
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
Page 101
... INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the ...
Page 102
... INT1IP INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP PEIE/GIEL GIE/GIEH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2009 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h ...
Page 103
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Note: Interrupt flag bits are set when an interrupt ...
Page 104
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39632E-page 102 R/W-1 U-0 R/W-1 — INTEDG2 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 ...
Page 106
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 107
... A TMR1 or TMR3 register capture occurred (must be cleared in software TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 108
... Disables the TMR1 overflow interrupt Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632E-page 106 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
Page 110
... Low priority Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632E-page 108 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 111
... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 112
... The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. DS39632E-page 110 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 113
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 9.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 112 © 2009 Microchip Technology Inc. ...
Page 115
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. ...
Page 116
... DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as ‘0’. IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as ‘0’. Description /4); available in EC, ECPLL and OSC © 2009 Microchip Technology Inc. ...
Page 117
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 ...
Page 118
... MOVLW 0Eh ; Set RB<4:0> as MOVWF ADCON1 ; digital I/O pins ; (required if config bit ; PBADEN is set) MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs © 2009 Microchip Technology Inc. delay. CY ...
Page 119
... Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type DIG LATB<0> data output; not affected by analog input. ...
Page 120
... SE0 PKTDIS USBEN RESUME SUSPND Description (3) (3) (3) Reset Bit 2 Bit 1 Bit 0 Values on page RB2 RB1 RB0 56 LATB1 LATB0 56 TRISB1 TRISB0 56 INT0IF RBIF 53 — RBIP 53 — INT2IF INT1IF 53 PCFG1 PCFG0 54 — SPPOWN SPPEN 57 WS2 WS1 WS0 57 — 57 © 2009 Microchip Technology Inc. ...
Page 121
... When the external transceiver is enabled, RC2 also serves as the output enable control to the transceiver. Additional information on configuring USB options is provided in Section 17.2.2.2 “External Transceiver”. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When enabling peripheral functions on PORTC pins other than RC4 and RC5, care should be taken in defin- ing the TRIS bits ...
Page 122
... Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. OUT DIG Synchronous serial clock output (EUSART module); takes priority over port data Synchronous serial clock input (EUSART module). Description © 2009 Microchip Technology Inc. ...
Page 123
... UCON — PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATC< ...
Page 124
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...
Page 125
... SPP7 1 1 P1D 0 Legend: OUT = Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: May be configured for tri-state during Enhanced PWM shutdown events. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATD<0> data output PORTD< ...
Page 126
... TRISD5 TRISD4 TRISD3 TRISD2 (1,2) — — RE3 RE2 DC1B1 DC1B0 CCP1M3 CCP1M2 — — — — Reset Bit 1 Bit 0 Values on page RD1 RD0 56 LATD1 LATD0 56 TRISD1 TRISD0 56 (3) (3) (3) RE1 RE0 56 CCP1M1 CCP1M0 55 SPPOWN SPPEN 57 © 2009 Microchip Technology Inc. ...
Page 127
... RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: Unimplemented in 28-pin devices; read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Config- uration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 128
... VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 — — — CSEN CLK1EN WS3 WS2 Description Reset Bit 1 Bit 0 Values on page (3) (3) (3) RE1 RE0 56 LATE1 LATE0 56 TRISE1 TRISE0 56 PCFG1 PCFG0 54 CM1 CM0 55 — SPPOWN SPPEN 57 WS1 WS0 57 © 2009 Microchip Technology Inc. ...
Page 129
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 130
... Sync with Internal Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0L TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 131
... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 11.3.1 SWITCHING PRESCALER ...
Page 132
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 130 © 2009 Microchip Technology Inc. ...
Page 133
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 134
... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 135
... T1OSI XTAL 32.768 kHz T1OSO Note: See the notes with Table 12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 136
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. a Special Event Trigger © 2009 Microchip Technology Inc. ...
Page 137
... CPFSGT hours RETURN CLRF hours RETURN © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 following a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L reg- ister pair while the clock is low, or one-half of the period of the clock source ...
Page 138
... DS39632E-page 136 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF RCIF TXIF SSPIF CCP1IF RCIE TXIE SSPIE CCP1IE RCIP TXIP SSPIP CCP1IP Reset Bit 1 Bit 0 Values on page INT0IF RBIF 53 TMR2IF TMR1IF 56 TMR2IE TMR1IE 56 TMR2IP TMR1IP TMR1CS TMR1ON 54 © 2009 Microchip Technology Inc. ...
Page 139
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 140
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 53 TMR2IF TMR1IF 56 TMR2IE TMR1IE 56 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
Page 141
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 142
... Clear TMR3 TMR3L 8 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 143
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 144
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 142 © 2009 Microchip Technology Inc. ...
Page 145
... Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode Note 1: These bits are not implemented on 28-pin devices and are read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. ...
Page 146
... Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropri- ate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction © 2009 Microchip Technology Inc. ...
Page 147
... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 148
... Set CCP1IF Output Compare Match Logic 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
Page 149
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 ...
Page 150
... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2009 Microchip Technology Inc. ...
Page 151
... The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EQUATION 15-3: PWM Resolution (max) Note: ...
Page 152
... PDC5 PDC4 PDC3 PDC2 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 53 PD POR BOR 54 TMR2IF TMR1IF 56 TMR2IE TMR1IE 56 TMR2IP TMR1IP 56 TRISB1 TRISB0 56 TRISC1 TRISC0 CCP1M1 CCP1M0 CCP2M1 CCP2M0 55 (2) (2) PSSBD0 55 (2) (2) (2) PDC1 PDC0 55 © 2009 Microchip Technology Inc. ...
Page 153
... PWM mode: P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 automatic shutdown and restart. The Enhanced features are discussed in detail in Section 16.4 “ ...
Page 154
... The latter is more generic but will work for either single or multi-output PWM. and Timer RC2 RD5 All PIC18F4455/4550 devices: CCP1 RD5/SPP5 P1A P1B P1A P1B and Section 15.3 “Compare for PWM Operation” or RD6 RD7 RD6/SPP6 RD7/SPP7 RD6/SPP6 RD7/SPP7 P1C P1D © 2009 Microchip Technology Inc. ...
Page 155
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 156
... The general relationship of the outputs in all configurations is summarized in Figure 16-2 and Figure 16-3. 9.77 kHz 39.06 kHz FFh FFh OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
Page 157
... Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 0 Duty Cycle Period (1) Delay Delay ...
Page 158
... Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Period (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
Page 159
... P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTD<7> data latches. The TRISC<2>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 160
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...
Page 161
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...
Page 162
... PDC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( cycles, between the scheduled and actual time for a PWM OSC OSC modules, a low level on the the PSSAC1:PSSAC0 and R/W-0 R/W-0 (1) (1) (1) PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 163
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
Page 164
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle ECCPASE Cleared by Firmware © 2009 Microchip Technology Inc. ...
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... Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
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... POR BOR 54 TMR2IP TMR1IP 56 TMR2IF TMR1IF 56 TMR2IE TMR1IE 56 TMR3IP CCP2IP 56 TMR3IF CCP2IF 56 TMR3IE CCP2IE 56 TRISB1 TRISB0 56 TRISC1 TRISC0 56 TRISD1 TRISD0 TMR1CS TMR1ON 54 54 T2CKPS1 T2CKPS0 TMR3CS TMR3ON CCP1M1 CCP1M0 55 (2) (2) PSSBD1 PSSBD0 55 (2) (2) (2) PDC1 PDC0 55 © 2009 Microchip Technology Inc. ...
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... Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1). 2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used not enable the internal regulator when using an external 3.3V supply. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The SIE can be interfaced directly to the USB, utilizing the internal transceiver can be connected through an external transceiver ...
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... USBEN bit when the module is in the suspended state may prevent the module from fully powering down. R/C-0 R/W-0 R/W-0 PKTDIS USBEN RESUME U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 SUSPND — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Bus Speed (full speed versus low speed) • On-Chip Pull-up Resistor Enable • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. ...
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... SIE that can’t be captured with the RCV signal. The combinations of states of these signals and their interpretation are listed in Table 17-1 and Table 17-2. R/W-0 R/W-0 PPB1 PPB0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... D+ D- Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.2.2.5 Ping-Pong Buffer Configuration The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong Buffering” ...
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... USB USTAT automatically issue a NAK back to the host. . USB FIGURE 17-4: USTAT from SIE 4-byte FIFO for USTAT Data Bus of clearing TRNIF additional FIFO is full, the SIE will USTAT FIFO Clearing TRNIF Advances FIFO © 2009 Microchip Technology Inc. ...
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... The last transaction was to the Odd BD bank 0 = The last transaction was to the Even BD bank bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available Even and Odd BD registers. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R-x R-x R-x ENDP1 ...
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... SIE. This bit remains set until it is cleared through firmware, or until the SIE is reset. R/W-0 R/W-0 R/W-0 EPHSHK EPCONDIS EPOUTEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared USB specifications identify R/W-0 R/W-0 EPINEN EPSTALL bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SIE should not be accessed by the microcontroller. A semaphore mechanism is used to determine the access to a particular buffer at any given time. This is discussed in Section 17.4.1.1 “Buffer Ownership”. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 17-5: Banks Banks 4 ...
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... BDs. From this point, the SIE updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count, BDnCNT, is updated. © 2009 Microchip Technology Inc. Contents Size of Block Starting Address ...
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... Either 0 Either, with error x Legend don’t care © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 the SIE. When enabled, it checks the data packet’s par- ity against the value of DTS (BDnSTAT<6>). If a packet arrives with an incorrect synchronization, the data will essentially be ignored. It will not be written to the USB RAM and the USB transfer complete interrupt flag will not be set ...
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... This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN = 1. DS39632E-page 176 R/W-x R/W-x R/W-x INCDIS DTSEN BSTALL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) R/W-x R/W-x BC9 BC8 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BC9:BC8: Byte Count 9 and 8 bits These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer and the actual number of bytes transmitted transfer. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The 10-bit byte count is distributed over two registers. ...
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... EP0 OUT Descriptor EP0 IN Descriptor EP1 OUT Even Descriptor EP1 OUT Odd Descriptor EP1 IN Even Descriptor EP1 IN Odd Descriptor EP15 IN Odd Descriptor 4F7h Available as Data RAM 4FFh Maximum Memory Used: 248 bytes Maximum BDs: 62 (BD0 to BD61) © 2009 Microchip Technology Inc. ...
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... Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings. 4: This bit is ignored unless DTSEN = 1. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 BDs Assigned to Endpoint Mode 1 ...
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... To Host IN Token Data From Host From Host OUT Token Empty Data Transaction SETUP DATA STATUS (1) Control Transfer USBIF To Host Set TRNIF ACK From Host Set TRNIF ACK To Host Set TRNIF ACK Transaction Complete SOF 1 ms Frame © 2009 Microchip Technology Inc. ...
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... Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and cannot be set or cleared by the user. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When the USB module is in the Low-Power Suspend mode (UCON<1> = 1), the SIE does not get clocked. ...
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... If user firmware clears the ACTVIF bit, the bit will not immediately become set again, even when there is continuous bus traffic. Bus traffic must cease long enough to generate another IDLEIF condition before another ACTVIF interrupt can be generated. © 2009 Microchip Technology Inc. ...
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... URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The values in this register only affect the propagation of an interrupt condition to the microcontroller’s inter- rupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt ...
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... Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a ‘0’. R/C-0 R/C-0 R/C-0 BTOEF DFN8EF CRC16EF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/C-0 R/C-0 CRC5EF PIDEF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the micro- controller’s interrupt logic. The flag bits are still set by ...
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... SELF-POWER ONLY Attach Sense I/O pin 100 kΩ USB V SS pin of the USB cable. BUS DUAL POWER EXAMPLE 100 kΩ Attach Sense I/O pin USB V SS © 2009 Microchip Technology Inc. ...
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... This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Refer to Section 18.0 “Streaming Parallel Port” for more information about the SPP ...
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... CRC5EF PIDEF 57 CRC5EE PIDEE 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 EPINEN EPSTALL 57 © 2009 Microchip Technology Inc. ...
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... Figure 17-9 shows an example of a transaction within a frame. FIGURE 17-13: USB LAYERS Interface Endpoint Endpoint © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.10.3 TRANSFERS There are four transfer types defined in the USB specification. • Isochronous: This type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured ...
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... USB device. In custom applications, a driver may need to be developed. Fortunately, drivers are available for most common host systems for the most common classes of devices. Thus, these drivers can be reused. © 2009 Microchip Technology Inc. the layer they support. ...
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... Microcontroller directly controls the SPP bit 0 SPPEN: SPP Enable bit 1 = SPP is enabled 0 = SPP is disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 In addition, the SPP can provide time multiplexed addressing information along with the data by using the second strobe output. Thus, the USB endpoint number can be written in conjunction with the data for that endpoint ...
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... The SPP data lines (SPP<7:0>) are equipped with internal pull-ups for applications that may leave the port in a high-impedance condition. The pull-ups are enabled using the control bit, RDPU (PORTE<7>). R/W-0 R/W-0 WS1 WS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES) USB Clock OESPP CSSPP CK1SPP CK2SPP Write Address SPP<7:0> 2 Wait States © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 DATA Write Data Read Data MOVWF SPPDATA MOVF SPPDATA, W Write Data 2 Wait States 2 Wait States ...
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... SPPEPS or SPPDATA registers do not overrun the wait time due to the wait state setting. Write USB endpoint number to SPP Write outbound USB data to SPP or read inbound USB data from SPP Byte 2 Byte 3 Byte n © 2009 Microchip Technology Inc. ...
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... Endpoint Address 15 • • • • 0001 0000 = Endpoint Address 0 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3. Read the data from the SPPDATA register; the data from the previous read operation is returned. The SPP automatically starts the read cycle for the next read. ...
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... RCIE TXIE SSPIE CCP1IE RCIP TXIP SSPIP CCP1IP (1,2) — — RE3 RE2 Reset Bit 1 Bit 0 Values on page SPPOWN SPPEN 57 WS1 WS0 57 ADDR1 ADDR0 57 DATA1 DATA0 57 TMR2IF TMR1IF 56 TMR2IE TMR1IE 56 TMR2IP TMR1IP 56 (3) (3) (3) RE1 RE0 56 © 2009 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 19.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of the SPI are supported ...
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... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...