PIC18F4431-I/P Microchip Technology, PIC18F4431-I/P Datasheet - Page 86

• Manufacturer Part Number: PIC18F4431-I/P
• Description: IC PIC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/P

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
FIGURE 8-2:
8.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
8.2.1
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers, regardless of EEPGD.
(See
When CFGS is clear, the EEPGD bit selects either
program Flash or data EEPROM memory.
DS39616D-page 86
Section 23.0 “Special Features of the
Control Registers
Note 1: The Table Pointer actually points to one of eight holding registers, the address of which is determined
TBLPTRU
EECON1 AND EECON2 REGISTERS
by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed
in
Table Pointer
Section 8.5 “Writing to Flash Program
TABLE WRITE OPERATION
TBLPTRH
(1)
TBLPTRL
Program Memory
(TBLPTR)
CPU”.)
Instruction: TBLWT*
Holding Registers
Program Memory
Memory”.
The FREE bit controls program memory erase opera-
tions. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
A write operation is allowed when the WREN bit
(EECON1<2>) is set. On power-up, the WREN bit is
clear. The WRERR bit (EECON1<3>) is set in hard-
ware when the WR bit (EECON1<1>) is set and
cleared when the internal programming timer expires
and the write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. The bit is
cleared in hardware at the completion of the write
operation.
Note:
Note:
During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset or a write operation was
attempted improperly.
The EEIF interrupt flag bit (PIR2<4>) is
set when the write is complete. It must be
cleared in software.
 2010 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT