ATMEGA162-16PU Atmel, ATMEGA162-16PU Datasheet - Page 34

IC AVR MCU 16K 16MHZ 5V 40DIP

ATMEGA162-16PU

Manufacturer Part Number
ATMEGA162-16PU
Description
IC AVR MCU 16K 16MHZ 5V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162-16PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Speed
16 MIPS
Eeprom Memory
512 Bytes
Input Output
35
Interface
JTAG/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 2-16-bit
Voltage, Range
2.7-5.5 V
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Using all 64KB
Locations of External
Memory
34
ATmega162/V
Since the external memory is mapped after the internal memory as shown in
64,256 Bytes of external memory are available by default (address space 0x0000 to 0x04FF is
reserved for internal memory). However, it is possible to take advantage of the entire external
memory by masking the higher address bits to zero. This can be done by using the XMMn bits
and control by software the most significant bits of the address. By setting Port C to output 0x00,
and releasing the most significant bits for normal Port Pin operation, the Memory Interface will
address 0x0000 - 0x1FFF. See code example below.
Note:
Care must be exercised using this option as most of the memory is masked away.
Assembly Code Example
C Code Example
#define OFFSET 0x2000
void XRAM_example(void)
{
unsigned char *p = (unsigned char *) (OFFSET + 1);
DDRC = 0xFF;
PORTC = 0x00;
SFIOR = (1<<XMM1) | (1<<XMM0);
*p = 0xaa;
SFIOR = 0x00;
*p = 0x55;
}
; OFFSET is defined to 0?2000 to ensure
; external memory access
; Configure Port C (addr?ss high byte) to
; output 0x00 when the p?ns are released
; for normal Port Pin op?ration
ldi
out
ldi
out
; release PC7:5
ldi
out
; write 0xAA to address ?x0001 of external
; memory
ldi
sts
; re-enable PC7:5 for ex?ernal memory
ldi
out
; store 0x55 to address ?OFFSET + 1) of
; external memory
ldi
sts
1. The example code assumes that the part specific header file is included.
r16, 0xFF
DDRC, r16
r16, 0x00
PORTC, r16
r16, (1<<XMM1)|(1<<XMM0)
SFIOR, r16
r16, 0xaa
0x0001+OFFSET, r16
r16, (0<<XMM1)|(0<<XMM0)
SFIOR, r16
r16, 0x55
0x0001+OFFSET, r16
(1)
(1)
Figure
2513K–AVR–07/09
11, only

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