DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 218

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

dsPIC30F3014/4013
Data Address Space ........................................................... 28
Data Converter Interface (DCI) Module ............................ 119
Data EEPROM Memory ...................................................... 47
DC Characteristics ............................................................ 169
DCI Module
DS70138F-page 216
Alignment .................................................................... 30
Alignment (Figure) ...................................................... 30
Effect of Invalid Memory Accesses (Table)................. 30
MCU and DSP (MAC Class)
Memory Map ............................................................... 28
Near Data Space ........................................................ 31
Software Stack ............................................................ 31
Spaces ........................................................................ 30
Width ........................................................................... 30
Erasing ........................................................................ 48
Erasing, Block ............................................................. 48
Erasing, Word ............................................................. 48
Protection Against Spurious Write .............................. 51
Reading....................................................................... 47
Write Verify ................................................................. 51
Writing ......................................................................... 49
Writing, Block .............................................................. 49
Writing, Word .............................................................. 49
BOR .......................................................................... 177
I/O Pin Input Specifications ....................................... 175
I/O Pin Output Specifications .................................... 175
Idle Current (I
LVDL ......................................................................... 176
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 177
Temperature and Voltage Specifications .................. 169
Bit Clock Generator................................................... 123
Buffer Alignment with Data Frames .......................... 125
Buffer Control ............................................................ 119
Buffer Data Alignment ............................................... 119
Buffer Length Control ................................................ 125
COFS Pin .................................................................. 119
CSCK Pin .................................................................. 119
CSDI Pin ................................................................... 119
CSDO Mode Bit ........................................................ 126
CSDO Pin ................................................................. 119
Data Justification Control Bit ..................................... 124
Device Frequencies for Common Codec
Digital Loopback Mode ............................................. 126
Enable ....................................................................... 121
Frame Sync Generator ............................................. 121
Frame Sync Mode Control Bits ................................. 121
I/O Pins ..................................................................... 119
Interrupts ................................................................... 126
Introduction ............................................................... 119
Master Frame Sync Operation .................................. 121
Operation .................................................................. 121
Operation During CPU Idle Mode ............................. 126
Operation During CPU Sleep Mode .......................... 126
Receive Slot Enable Bits........................................... 124
Receive Status Bits ................................................... 125
Register Map............................................................. 128
Sample Clock Edge Control Bit................................. 124
Slave Frame Sync Operation .................................... 122
Slot Enable Bits Operation with Frame Sync ............ 124
Slot Status Bits.......................................................... 126
Synchronous Data Transfers .................................... 124
Instructions Example........................................... 29
CSCK Frequencies (Table)............................... 123
IDLE
) .................................................... 172
DD
)............................................. 171
PD
) ........................................ 173
Development Support ....................................................... 165
Device Configuration
Device Configuration Registers
Device Overview................................................................... 9
Disabling the UART .......................................................... 103
Divide Support .................................................................... 16
DSP Engine ........................................................................ 17
Dual Output Compare Match Mode .................................... 86
E
Electrical Characteristics .................................................. 169
Enabling and Setting Up UART
Enabling and Setting up UART
Enabling the UART ........................................................... 103
Equations
Errata .................................................................................... 8
Exception Sequence
External Clock Timing Requirements ............................... 179
External Interrupt Requests ................................................ 64
F
Fast Context Saving ........................................................... 64
Flash Program Memory ...................................................... 41
I
I/0 Ports
I/O Pin Specifications
I/O Ports.............................................................................. 53
Timing Requirements
Transmit Slot Enable Bits ......................................... 124
Transmit Status Bits.................................................. 125
Transmit/Receive Shift Register ............................... 119
Underflow Mode Control Bit...................................... 126
Word-Size Selection Bits .......................................... 121
Register Map ............................................................ 156
FBORPOR ................................................................ 154
FGS .......................................................................... 154
FOSC........................................................................ 154
FWDT ....................................................................... 154
Instructions (Table) ..................................................... 16
Multiplier ..................................................................... 19
Continuous Pulse Mode.............................................. 86
Single Pulse Mode...................................................... 86
AC............................................................................. 178
DC ............................................................................ 169
Alternate I/O ............................................................. 103
Setting up Data, Parity and
ADC Conversion Clock ............................................. 131
Baud Rate................................................................. 105
Bit Clock Frequency.................................................. 123
COFSG Period.......................................................... 121
Serial Clock Rate ........................................................ 94
Time Quantum for Clock Generation ........................ 115
Trap Sources .............................................................. 62
Type A Timer ............................................................ 185
Type B Timer ............................................................ 186
Type C Timer ............................................................ 186
Register Map .............................................................. 55
Input.......................................................................... 175
Output ....................................................................... 175
Parallel (PIO) .............................................................. 53
AC-Link Mode................................................... 192
Multichannel, I
Stop Bit Selections ........................................... 103
2
S Modes................................... 190
© 2008 Microchip Technology Inc.