PIC24HJ64GP510-I/PT Microchip Technology, PIC24HJ64GP510-I/PT Datasheet - Page 183
![IC PIC MCU FLASH 32KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ64GP510-I/PT
Manufacturer Part Number
PIC24HJ64GP510-I/PT
Description
IC PIC MCU FLASH 32KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ64GP510-I/PT
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
No. Of Pwm Channels
8
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
A/d Bit Size
12 bit
A/d Channels Available
32
Height
1 mm
Length
12 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
12 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip
Quantity:
104
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
MICROCHIP
Quantity:
455
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
18.5
18.5.1
The CAN module has up to eight transmit buffers,
located in DMA RAM. These 8 buffers need to be con-
figured as transmit buffers by setting the corresponding
TX/RX buffer selection (TXENn or TXENm) bit in a
CiTRmnCON register. The overall size of the CAN
buffer area in DMA RAM is selectable by the user and
is
(CiFCTRL<15:13>).
Each transmit buffer occupies 16 bytes of data. Eight of
the bytes are the maximum 8 bytes of the transmitted
message. Five bytes hold the standard and extended
identifiers and other message arbitration information.
The last byte is unused.
18.5.2
Transmit priority is a prioritization within each node of
the pending transmittable messages. There are four
levels of transmit priority. If the TXnPRI<1:0> bits (in
CiTRmnCON) for a particular message buffer are set to
‘11’, that buffer has the highest priority. If the
TXnPRI<1:0> bits for a particular message buffer are
set to ‘10’ or ‘01’, that buffer has an intermediate prior-
ity. If the TXnPRI<1:0> bits for a particular message
buffer are ‘00’, that buffer has the lowest priority. If two
or more pending messages have the same priority, the
messages are transmitted in decreasing order of buffer
index.
18.5.3
To initiate transmission of the message, the TXREQn
bit (in CiTRmnCON) must be set. The CAN bus module
resolves any timing conflicts between the setting of the
TXREQn bit and the Start-of-Frame (SOF), ensuring
that if the priority was changed, it is resolved correctly
before the SOF occurs. When TXREQn is set, the
TXABTn, TXLARBn and TXERRn flag bits are
automatically cleared.
Setting the TXREQn bit simply flags a message buffer
as enqueued for transmission. When the module
detects an available bus, it begins transmitting the
message which has been determined to have the
highest priority.
If the transmission completes successfully on the first
attempt, the TXREQn bit is cleared automatically and
an interrupt is generated if TXnIE was set.
If the message transmission fails, one of the error con-
dition flags will be set and the TXREQn bit will remain
set, indicating that the message is still pending for
transmission. If the message encountered an error
condition during the transmission attempt, the TXERRn
bit will be set and the error condition may cause an
interrupt. If the message loses arbitration during the
transmission attempt, the TXLARBn bit is set. No
interrupt is generated to signal the loss of arbitration.
© 2006 Microchip Technology Inc.
defined
Message Transmission
TRANSMIT BUFFERS
TRANSMIT MESSAGE PRIORITY
TRANSMISSION SEQUENCE
by
the
DMABS<2:0>
Preliminary
bits
18.5.4
If the RTRENn bit (in the CiTRmnCON register) for a
particular transmit buffer is set, the hardware automat-
ically transmits the data in that buffer in response to
remote transmission requests matching the filter that
points to that particular buffer. The user does not need
to manually initiate a transmission in this case.
18.5.5
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer. Set-
ting the ABAT bit (CiCTRL1<12>) will request an abort
of all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit and the TXnIF flag is not
automatically set.
18.5.6
The CAN module will detect the following transmission
errors:
• Acknowledge Error
• Form Error
• Bit Error
These transmission errors will not necessarily generate
an interrupt, but are indicated by the transmission error
counter. However, each of these errors will cause the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Interrupt Flag
register is set.
AUTOMATIC PROCESSING OF
REMOTE TRANSMISSION
REQUESTS
ABORTING MESSAGE
TRANSMISSION
TRANSMISSION ERRORS
PIC24H
DS70175C-page 181