PIC24HJ64GP510-I/PT Microchip Technology, PIC24HJ64GP510-I/PT Datasheet - Page 51
![IC PIC MCU FLASH 32KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ64GP510-I/PT
Manufacturer Part Number
PIC24HJ64GP510-I/PT
Description
IC PIC MCU FLASH 32KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ64GP510-I/PT
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
No. Of Pwm Channels
8
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
A/d Bit Size
12 bit
A/d Channels Available
32
Height
1 mm
Length
12 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
12 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip
Quantity:
104
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
MICROCHIP
Quantity:
455
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 3-32:
3.3.3
Move instructions provide a greater degree of address-
ing flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, move instructions also support Register Indirect
with Register Offset Addressing mode, also referred to
as Register Indexed mode.
In summary, the following Addressing modes are
supported by move instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
3.3.4
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, the source of an oper-
and or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
© 2006 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
Note:
Note:
Addressing Mode
MOVE INSTRUCTIONS
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared between both source and
destination (but typically only used by
one).
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
OTHER INSTRUCTIONS
FUNDAMENTAL ADDRESSING MODES SUPPORTED
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
The sum of Wn and a literal forms the EA.
Preliminary
3.4
The PIC24H architecture uses a 24-bit wide program
space and a 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24H architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
• Remapping a portion of the program space into
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated from time to time. It also allows
access to all bytes of the program word. The remap-
ping method allows an application to access a large
block of data on a read-only basis, which is ideal for
look ups from a large table of static data. It can only
access the least significant word of the program word.
3.4.1
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
or words anywhere in the program space
the data space (Program Space Visibility)
Description
Interfacing Program and Data
Memory Spaces
ADDRESSING PROGRAM SPACE
PIC24H
DS70175C-page 49