ATMEGA324P-20PU Atmel, ATMEGA324P-20PU Datasheet - Page 14
ATMEGA324P-20PU
Manufacturer Part Number
ATMEGA324P-20PU
Description
IC MCU AVR 32K FLASH 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA324P-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/JTAG/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
1 KB
Height
4.83 mm
Length
52.58 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
13.97 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (10Mb)
4.5.1
4.5.2
4.6
8011O–AVR–07/10
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Stack pointer Low
RAMPZ – Extended Z-pointer Register for ELPM/SPM
Note:
Table 4-2.
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.
Figure 4-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-5 on page 15
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit (Individually)
Bit (Z-pointer)
1. Initial values respectively for the ATmega164P/324P/644P.
Stack Pointer size
The Z-pointer used by ELPM and SPM
RAMPZ7
R/W
R/W
SP7
15
7
0
R
–
7
0
1
ATmega164P
ATmega324P
ATmega644P
23
7
Device
shows the parallel instruction fetches and instruction executions enabled
RAMPZ6
R/W
SP6
R/W
RAMPZ
14
6
0
R
–
6
0
1
RAMPZ5
R/W
SP5
R/W
CPU
5
0
13
R
–
5
0
1
16
0
, directly generated from the selected clock source for the
RAMPZ4
0/0/1
R/W
SP12
SP4
R/W
R/W
4
0
12
4
1
(1)
15
7
ATmega164P/324P/644P
RAMPZ3
R/W
0/1/0
SP11
SP3
R/W
R/W
3
0
11
3
1
(1)
ZH
RAMPZ2
R/W
1/0/0
SP10
2
0
SP2
R/W
R/W
10
Stack Pointer size
2
1
(1)
0
8
SP[10:0]
SP[11:0]
SP[12:0]
RAMPZ1
R/W
SP9
SP1
R/W
R/W
1
0
9
1
0
1
7
7
RAMPZ0
R/W
SP8
SP0
R/W
R/W
0
0
8
0
0
1
ZL
RAMPZ
SPH
SPL
0
0
14
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