ATmega32 Atmel Corporation, ATmega32 Datasheet

no-image

ATmega32

Manufacturer Part Number
ATmega32
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega32

Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega32-16AC
Manufacturer:
COMPAL
Quantity:
500
Part Number:
ATmega32-16AC
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega32-16AI
Manufacturer:
Atmel
Quantity:
10 000
Company:
Part Number:
ATmega32-16AI
Manufacturer:
ATMEL
Quantity:
5
Company:
Part Number:
ATmega32-16AI
Manufacturer:
ATMEL
Quantity:
62
Part Number:
ATmega32-16AI
Manufacturer:
ATMEL
Quantity:
10
Part Number:
ATmega32-16AJ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega32-16AQ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega32-16AQR
Manufacturer:
Atmel
Quantity:
10 000
Company:
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
229
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
56
Part Number:
ATmega32-16MU
Manufacturer:
ATMEL
Quantity:
300
Company:
Part Number:
ATmega32-16PU
Manufacturer:
ATMEL
Quantity:
62
Part Number:
ATmega32-16PU
Manufacturer:
ATMEL
Quantity:
2 000
Part Number:
ATmega32-AU
Manufacturer:
ATMEL
Quantity:
1 000
Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
Power Consumption at 1MHz, 3V, 25°C
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
– 32Kbytes of In-System Self-programmable Flash program memory
– 1024Bytes EEPROM
– 2Kbytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– 2.7V - 5.5V for ATmega32L
– 4.5V - 5.5V for ATmega32
– 0 - 8MHz for ATmega32L
– 0 - 16MHz for ATmega32
– Active: 1.1mA
– Idle Mode: 0.35mA
– Power-down Mode: < 1µA
True Read-While-Write Operation
Mode
and Extended Standby
In-System Programming by On-chip Boot Program
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 32KBytes
In-System
Programmable
Flash
ATmega32
ATmega32L
2503Q–AVR–02/11

Related parts for ATmega32

ATmega32 Summary of contents

Page 1

... PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for ATmega32L – 4.5V - 5.5V for ATmega32 • Speed Grades – 8MHz for ATmega32L – 16MHz for ATmega32 • Power Consumption at 1MHz, 3V, 25°C – Active: 1.1mA – Idle Mode: 0.35mA – Power-down Mode: < 1µA ® ® ...

Page 2

... Pin Configurations Figure 1. Pinout ATmega32 2503Q–AVR–02/11 PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 ...

Page 3

... Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram VCC GND AVCC AREF 2503Q–AVR–02/11 ® ...

Page 4

... Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effec- tive solution to many embedded control applications. The Atmel AVR ATmega32 is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega32 as listed on 57. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 2503Q–AVR–02/11 1. ATmega32(L) 6 ...

Page 7

... These code examples assume that the part specific header file is included before Examples compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documen- tation for more details. 2503Q–AVR–02/11 ATmega32(L) 7 ...

Page 8

... The main function of the Program Flash Counter and Control Program Memory Instruction General Purpose Register Registrers Instruction Decoder Control Lines SRAM EEPROM I/O Lines ATmega32(L) Data Bus 8-bit Status Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data I/O Module 2 I/O Module n 8 ...

Page 9

... Some implementa- tions of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 2503Q–AVR–02/11 ® ® AVR ALU operates in direct connection with all the 32 general ATmega32(L) 9 ...

Page 10

... Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2503Q–AVR–02/ R/W R/W R/W R/W R ⊕ V ATmega32( SREG R/W R/W R ...

Page 11

... R14 Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4, each register is also assigned a data memory address, mapping them ATmega32(L) ® ® AVR Enhanced RISC instruction set. In order to 0 Addr. $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register Low Byte ...

Page 12

... R31 ($1F SP15 SP14 SP13 SP12 SP11 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R ATmega32(L) Figure R26 ($1A R28 ($1C R30 ($1E SP10 SP9 SP8 SPH SP3 SP2 SP1 SP0 SPL R/W R/W ...

Page 13

... Register File single clock cycle an ALU clk CPU Total Execution Time Result Write Back ® ® AVR provides several different interrupt sources. These interrupts and the separate for details. ATmega32( “Interrupts” on page T4 T4 “Memory Pro- 44 ...

Page 14

... EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2503Q–AVR–02/11 “Boot Loader Support – Read-While-Write Self- 244. ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ ATmega32(L) “Interrupts” on page 44 for more 14 ...

Page 15

... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2503Q–AVR–02/11 ; set global interrupt enable ATmega32(L) ® ® AVR interrupts is four clock cycles ...

Page 16

... Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega32 Pro- gram Counter (PC bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in 244 ...

Page 17

... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of internal data SRAM in the ATmega32 are all accessible through all these addressing modes. The Register File is described in Figure 9. Data Memory Map 2503Q– ...

Page 18

... SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega32 contains 1024 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles ...

Page 19

... Read/Write Initial Value • Bits 15..10 – Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. • Bits 9..0 – EEAR9..0: EEPROM Address The EEPROM Address Registers 1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023 ...

Page 20

... The examples 2503Q–AVR–02/11 Number of Calibrated RC Symbol Oscillator Cycles 1. Uses 1MHz clock, independent of CKSEL Fuse setting. ATmega32(L) for details about boot Table 1 lists the typical pro- (1) Typ Programming Time 8448 8.5ms “ ...

Page 21

... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega32(L) 21 ...

Page 22

... Read data from data register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, ATmega32(L) 22 ...

Page 23

... I/O Memory The I/O space definition of the ATmega32 is shown in All ATmega32 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working regis- ters and the I/O space. I/O Registers within the address range $00 - $1F are directly bit- accessible using the SBI and CBI instructions ...

Page 24

... AVR Clock I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC External Clock Oscillator Oscillator is halted, enabling TWI address reception in all sleep modes. I/O ATmega32(L) Figure CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog ...

Page 25

... In-System or Parallel Programmer. 2503Q–AVR–02/11 (1) 1. For all fuses “1” means unprogrammed while “0” means programmed. 327. = 5.0V) Typ Time-out (V CC 4.1ms 65ms ATmega32(L) CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 = 3.0V) Number of Cycles CC 4.3ms ...

Page 26

... This option should not be used with crystals, only with ceramic resonators. ATmega32(L) Figure 12. Either a quartz crystal or a Table 4. For ceramic resonators, the XTAL2 XTAL1 GND Table 4. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...

Page 27

... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATmega32(L) Additional Delay from Reset ( ...

Page 28

... CK 4.1ms ( 65ms 32K CK 65ms 1. These options should only be used if frequency stability at start-up is not important for the application ATmega32(L) = 5.0V) Recommended Usage Fast rising power or BOD enabled Slowly rising power Stable frequency at start-up Reserved NC XTAL2 XTAL1 GND Figure 13 can be Table 7 ...

Page 29

... This option should not be used when operating close to the maximum frequency of the device. and Temperature. When this Oscillator is used as the CC 258. CKSEL3..0 (1) 0001 0010 0011 0100 1. The device is shipped with this option selected. ATmega32(L) Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 = 5.0V) Recommended Usage – BOD enabled Fast rising power ...

Page 30

... The device is shipped with this option selected CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value Min Frequency in Percentage of Nominal Frequency (%) $00 50 $7F 75 100 ATmega32(L) from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4.1ms Fast rising power 65ms Slowly rising power Reserved CAL3 CAL2 ...

Page 31

... Start-up Time from Additional Delay Power-down and Power-save The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF. ATmega32(L) from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4.1ms ...

Page 32

... Bits [6:4] – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the six available sleep modes as shown in Table 13. Sleep Mode Select SM2 Note: 2503Q–AVR–02/11 presents the different clock systems in the ATmega32, and their distribu SM2 SM1 SM0 R/W R/W R/W R/W 0 ...

Page 33

... Timer/Counter2 if clocked asynchronously. 2503Q–AVR–02/11 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page , allowing operation only of asynchronous ASY ATmega32(L) , and clk , while allowing the CPU FLASH “External Interrupts” on page 66 25. 33 ...

Page 34

... Active Clock domains Oscillators (2) X ( (1) 1. External Crystal or resonator selected as clock source bit in ASSR is set. 3. Only INT2 or level interrupt INT1 and INT0. ATmega32(L) Wake-up Sources ( ( (2) (3) ...

Page 35

... Watchdog Timer. ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 53 /2, the input buffer will use excessive power. CC ATmega32(L) for details on how to for details on how to “Internal Volt- ) are stopped, the input buffers of the ADC ...

Page 36

... CKSEL Fuses. The different selec- tions for the delay period are presented in Reset Sources The ATmega32 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...

Page 37

... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega32L and BODLEVEL = 0 for ATmega32. BODLEVEL = 1 is not applicable for ATmega32. ATmega32(L) DATA BUS ...

Page 38

... The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT TIME-OUT INTERNAL RESET V POT V CC RESET TIME-OUT INTERNAL RESET ATmega32(L) is below the detection level. The RST t TOUT 38 ...

Page 39

... Time-out period t Figure 18. External Reset During Operation Brown-out Detection ATmega32 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...

Page 40

... Reset Flags. 2503Q–AVR–02/11 for details on operation of the Watchdog Timer JTD ISC2 – JTRF R/W R ATmega32( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description . Refer to TOUT 40 ...

Page 41

... Internal Voltage ATmega32 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference The voltage reference has a start-up time that may influence the way it should be used. The ...

Page 42

... Initial Value • Bits [7:5] – Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

Page 43

... Write logical one to WDTOE and WDE in r16, WDTCR ori r16, (1<<WDTOE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* reset WDT */ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega32(L) 43 ...

Page 44

... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32. For a general explanation of the AVR interrupt handling, refer to page 13. Interrupt Vectors in ATmega32 Table 18. Reset and Interrupt Vectors Vector No Notes: Table 19 BOOTRST and IVSEL settings ...

Page 45

... Table 19. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega32 is: Address $000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 ...

Page 46

... RESET: ldi r16,high(RAMEND) ; Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ATmega32(L) Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...

Page 47

... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 244 ATmega32( – ...

Page 48

... Move_interrupts(void 2503Q–AVR–02/11 ; Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret /* Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); ATmega32(L) 48 ...

Page 49

... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O Ports” on page 54. Refer to the individual module sections for a full description of the alter- ATmega32(L) Figure 22. Refer to “Electrical Charac Logic See Figure 23 "General Digital I/O" for Details 64 ...

Page 50

... SLEEP: SLEEP CONTROL clk : I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 64, the DDxn bits are accessed at the DDRx I/O address, the ATmega32(L) Figure DDxn Q CLR RESET Q ...

Page 51

... Output Figure 23, the PINxn Register bit and the preceding latch consti- and t pd,max SYSTEM CLK XXX SYNC LATCH PINxn r17 and t pd,max pd,min ATmega32(L) Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...

Page 52

... INSTRUCTIONS SYNC LATCH 2503Q–AVR–02/11 Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the through the synchronizer is one system clock period. pd r16 out PORTx, r16 PINxn r17 ATmega32(L) 0xFF nop in r17, PINx 0x00 t pd 0xFF 52 ...

Page 53

... Figure 23, the digital input signal can be clamped to ground at the input of the /2. CC ATmega32(L) “Alternate Port Functions” on page 54. 53 ...

Page 54

... DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. All other signals are unique for each pin. ATmega32(L) Figure 23 can be overridden by alter- PUOExn PUOVxn ...

Page 55

... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog Input/ output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. ATmega32(L) Fig- 55 ...

Page 56

... ADC1 (ADC input channel 1) PA0 ADC0 (ADC input channel 0) and Table 24 relate the alternate functions of Port A to the overriding signals shown in 54. PA7/ADC7 PA6/ADC6 – ADC7 INPUT ADC6 INPUT ATmega32( – ACME PUD PSR2 PSR10 R R/W R/W R/W R ...

Page 57

... SS (SPI Slave Select Input) AIN1 (Analog Comparator Negative Input) OC0 (Timer/Counter0 Output Compare Match Output) AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) T1 (Timer/Counter1 External Counter Input) T0 (Timer/Counter0 External Counter Input) XCK (USART External Clock Input/Output) ATmega32(L) PA1/ADC1 PA0/ADC0 ...

Page 58

... Figure 26 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 2503Q–AVR–02/11 and Table 27 relate the alternate functions of Port B to the overriding signals shown in 54. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, ATmega32(L) 58 ...

Page 59

... OC0 ENABLE 0 OC0 0 0 INT2 ENABLE 0 1 – INT2 INPUT AIN1 INPUT AIN0 INPUT ATmega32(L) PB5/MOSI PB4/SS SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR 0 SPI MSTR OUTPUT ...

Page 60

... TOSC1 (Timer Oscillator Pin 1) TDI (JTAG Test Data In) TDO (JTAG Test Data Out) TMS (JTAG Test Mode Select) TCK (JTAG Test Clock) SDA (Two-wire Serial Bus Data Input/Output Line) SCL (Two-wire Serial Bus Clock Line) ATmega32(L) Table 28. If the JTAG interface is enabled, 60 ...

Page 61

... Port C to the overriding signals shown in 54. PC7/TOSC2 PC6/TOSC1 AS2 AS2 0 0 AS2 AS2 AS2 AS2 0 0 – – T/C2 OSC OUTPUT T/C2 OSC INPUT ATmega32(L) PC5/TDI PC4/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI – 61 ...

Page 62

... ICP1 (Timer/Counter1 Input Capture Pin) OC1A (Timer/Counter1 Output Compare A Match Output) OC1B (Timer/Counter1 Output Compare B Match Output) INT1 (External Interrupt 1 Input) INT0 (External Interrupt 0 Input) TXD (USART Output Pin) RXD (USART Input Pin) ATmega32(L) (1) PC1/SDA PC0/SCL TWEN TWEN PORTC1 • PUD PORTC0 • ...

Page 63

... Port D to the overriding signals shown in 54. PD7/OC2 PD6/ICP1 OC2 ENABLE 0 OC2 – ICP1 INPUT – – ATmega32(L) PD5/OC1A PD4/OC1B OC1A ENABLE OC1B ENABLE OC1A OC1B – – – – 63 ...

Page 64

... PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R ATmega32(L) PD1/TXD PD0/RXD TXEN RXEN 0 PORTD0 • PUD TXEN RXEN 1 0 TXEN 0 TXD – RXD – – PORTA3 PORTA2 PORTA1 PORTA0 R/W ...

Page 65

... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega32( PINB3 PINB2 PINB1 PINB0 N/A N/A N/A N PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 ...

Page 66

... The low level of INT1 generates an interrupt request. 1 Any logical change on INT1 generates an interrupt request. 0 The falling edge of INT1 generates an interrupt request. 1 The rising edge of INT1 generates an interrupt request. ATmega32(L) 24. Low level interrupts on INT0/INT1 and the 287. The MCU will “System Clock and ...

Page 67

... Table 36 will generate an interrupt. Shorter pulses are not guaranteed to Parameter Minimum pulse width for asynchronous external interrupt INT1 INT0 INT2 – R/W R/W R ATmega32( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description Condition Min Typ Max ...

Page 68

... INTF2 Flag. See Modes” on page 53 2503Q–AVR–02/ INTF1 INTF0 INTF2 – R/W R/W R for more information. ATmega32( – – – – GIFR “Digital Input Enable and Sleep 68 ...

Page 69

... The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). 2503Q–AVR–02/11 “Pinout ATmega32” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...

Page 70

... Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clk Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source ATmega32(L) 84. TOVn (Int. Req.) Clock Select Edge Detector clk ...

Page 71

... A CPU write overrides (has priority over) all counter clear or T0 73. (See “Modes of Operation” on page shows a block diagram of the output compare unit. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega32(L) 73.). TCNTn OCFn (Int.Req.) OCn COMn1:0 71 ...

Page 72

... COM01:0 bits are shown. When referring to the OC0 state, the reference is for the internal OC0 Register, not the OC0 pin System Reset occur, the OC0 Register is reset to “0”. 2503Q–AVR–02/11 ATmega32(L) Figure 30 shows a simplified schematic of 72 ...

Page 73

... In normal operation the Timer/Counter Overflow Flag ( 2503Q–AVR–02/11 COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 80. Table 39 on page 81. For fast PWM mode, refer to Table 41 on page Figure 77. ATmega32( OCn PORT D Q DDR Table 40 on page 81. 72.). ...

Page 74

... MAX to 0x00. 2503Q–AVR–02/11 0 Flag in this case behaves like a ninth TOV 0 Flag, the timer resolution can be increased by software. TOV Figure clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + ATmega32(L) 31. The counter value (TCNT0) OCn Interrupt Flag Set (COMn1 OC0 clk_I ...

Page 75

... Figure 32. The TCNT0 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period OCnPWM ATmega32(L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 Table 40 on page 81). The actual OC0 value will ...

Page 76

... The PWM waveform is generated by clearing (or setting) the OC0 Register at the compare match 2503Q–AVR–02/ Table 41 on page ATmega32(L) Figure 33. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 81) ...

Page 77

... OCn has a transition from high to low even though there Figure 34 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega32(L) f clk_I/O = ----------------- - ⋅ N 510 Figure 33. When the OCR0A value is MAX the ...

Page 78

... OCFn Figure 37 2503Q–AVR–02/11 I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ATmega32(L) /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 78 ...

Page 79

... Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn 2503Q–AVR–02/11 /8) I/O Tn /8) I/O TOP - 1 ATmega32(L) TOP BOTTOM TOP BOTTOM + 1 79 ...

Page 80

... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega32( WGM01 CS02 CS01 CS00 R/W ...

Page 81

... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See 76 for more details. ATmega32(L) (1) “Fast PWM Mode” on page 75 (1) “Phase Correct PWM Mode” on page ...

Page 82

... External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R ATmega32( R/W R/W R/W R R/W R/W R/W R OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R TCNT0 OCR0 ...

Page 83

... Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. 2503Q–AVR–02/ OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R/W R ATmega32( TOV1 OCF0 TOV0 TIFR R/W R/W R ...

Page 84

... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATmega32(L) /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 38 ). The latch ...

Page 85

... This bit will always be read as zero. 2503Q–AVR–02/11 I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ADTS2 ADTS1 ADTS0 R/W R/W R ATmega32(L) (1) T1 T1/T0) is shown in Figure – ACME PUD PSR2 PSR10 R R/W R/W R/W ...

Page 86

... I/O pins, refer to bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 2503Q–AVR–02/11 Figure 1 on page 2. CPU accessible I/O Registers, including I/O 107. ATmega32(L) Figure 40. For the actual 86 ...

Page 87

... Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1 on page 2, Timer/Counter1 pin placement and description. The compare match event will also set the Compare Match ATmega32(L) (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int ...

Page 88

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Regis- ter. The assignment is dependent of the mode of operation. ATmega32(L) (See 88 ...

Page 89

... Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See “About Code Examples” on page ATmega32( ...

Page 90

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page ATmega32( ...

Page 91

... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page “Timer/Counter0 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. ATmega32(L) 7. 84. 91 ...

Page 92

... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega32(L) TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 97 ...

Page 93

... ICR1L. 2503Q–AVR–02/11 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ATmega32(L) Figure 42. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) ...

Page 94

... I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals 2503Q–AVR–02/11 89. ATmega32(L) “Accessing 16-bit Registers” (Figure 38 on page 84). The edge detector is also 94 ...

Page 95

... The small “n” in the register and bit DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega32(L) 97.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...

Page 96

... PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin System Reset occur, the OC1x Register is reset to “0”. 2503Q–AVR–02/11 89. ATmega32(L) “Accessing 16-bit Registers” Figure 44 shows a simplified 96 ...

Page 97

... COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O See “16-bit Timer/Counter Register Description” on page 107. Table 44 on page “Timer/Counter Timing Diagrams” on page ATmega32( OCnx OCnx Pin DDR Table 44, Table 45 and Table 46 107. For fast PWM mode refer to Table 46 on page 96 ...

Page 98

... TCNT1, the counter will miss the compare match. The counter will then have to count to its max- imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. 2503Q–AVR–02/11 Figure ATmega32(L) 45. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 ...

Page 99

... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 2503Q–AVR–02/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ FPWM ATmega32(L) f clk_I/O ⋅ OCRnA TOP log 1 + ---------------------------------- - log Figure 46 ...

Page 100

... OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). 2503Q–AVR–02/ ATmega32(L) OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set OCnA Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

Page 101

... TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter- rupt Flag will be set when a compare match occurs. 2503Q–AVR–02/11 f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I TOP log + ---------------------------------- - PCPWM log ATmega32(L) ) Figure 47. The figure 101 ...

Page 102

... OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when 2503Q–AVR–02/ ATmega32(L) OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set ...

Page 103

... PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 2503Q–AVR–02/11 f OCnxPCPWM 48). R PFCPWM Figure 48. The figure shows phase and frequency correct PWM ATmega32(L) f clk_I/O = --------------------------- - ⋅ ⋅ TOP ( ) TOP ...

Page 104

... PWM mode. If the OCR1x is set equal to BOTTOM the 2503Q–AVR–02/ shows the output generated is, in contrast to the phase correct mode, symmetrical f OCnxPFCPWM ATmega32(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) ...

Page 105

... OCRnx - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O OCRnx - 1 shows the count sequence close to TOP in various modes. When using phase and ATmega32( therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value OCRnx ...

Page 106

... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega32(L) TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 ...

Page 107

... R/W R/W R/W R Table 44 COM1A0/COM1B0 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM ATmega32( FOC1A FOC1B WGM11 WGM10 W W R/W R shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected ...

Page 108

... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 101. ATmega32(L) (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OC1A/OC1B disconnected ...

Page 109

... PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ATmega32(L) (See “Modes of Operation” on page Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF ...

Page 110

... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. ATmega32( WGM12 CS12 CS11 CS10 TCCR1B R/W R/W R/W R Figure ...

Page 111

... R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R/W R See “Accessing 16-bit Registers” on page 89 ICR1[15:8] ICR1[7:0] R/W R/W R/W R/W R ATmega32( TCNT1H TCNT1L R/W R/W R See “Accessing 16-bit OCR1AH OCR1AL R/W R/W R OCR1BH OCR1BL R/W R/W R ...

Page 112

... OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega32( OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R ...

Page 113

... TOV1 Flag is set when the timer overflows. Refer to behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 2503Q–AVR–02/11 ATmega32(L) Table 47 on page 109 for the TOV1 Flag 113 ...

Page 114

... Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- tive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 2503Q–AVR–02/11 “Pinout ATmega32” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...

Page 115

... Increment or decrement TCNT2 by 1. Selects between increment and decrement. Clear TCNT2 (set all bits to zero). Timer/Counter clock. Signalizes that TCNT2 has reached maximum value. ATmega32(L) See “Output Compare Table 49 are also used extensively 128. For details on clock sources and prescaler, see TOVn (Int ...

Page 116

... A CPU write overrides (has priority over) all counter clear or T2 118. can be used for generating a CPU interrupt. TOV2 118). Figure 55 shows a block diagram of the output compare unit. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega32(L) (“Modes of Operation” TCNTn OCFn (Int.Req.) OCxy COMn1:0 116 ...

Page 117

... Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. 2503Q–AVR–02/11 ATmega32(L) Figure 56 shows a simplified schematic of 117 ...

Page 118

... COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 125. Table 51 on page 126. For fast PWM mode, refer to Table 53 on page “Timer/Counter Timing Diagrams” on page ATmega32( OCn OCn Pin PORT D Q ...

Page 119

... The OC2 value will not be visible on the port pin unless the data direction for the 2503Q–AVR–02/11 TOV2 Flag, the timer resolution can be increased by software. There TOV2 Figure ATmega32(L) ) will be set in the same TOV2 Flag in this case behaves like a ninth 57. The counter value (TCNT2) OCn Interrupt Flag Set (COMn1 119 ...

Page 120

... OCn Figure 58. The TCNT2 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period set each time the counter reaches MAX. If the inter- TOV2 ATmega32(L) f clk_I/O ---------------------------------------------- - ⋅ ⋅ OCRn 1 + Flag is set in the same timer clock cycle that the ...

Page 121

... The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. 2503Q–AVR–02/11 ATmega32(L) f clk_I/O f ...

Page 122

... OCn OCn Period 1 TOV2 f OCnPCPWM Figure 59 OCn has a transition from high to low even though there ATmega32(L) OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 set each time the counter reaches BOTTOM. The Table 53 on page 126) ...

Page 123

... Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. ATmega32(L) should be replaced by I/O MAX BOTTOM /8) clk_I/O MAX BOTTOM ) T2 BOTTOM + 1 BOTTOM + 1 ...

Page 124

... Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O (clk TCNTn (CTC) OCRn OCFn 2503Q–AVR–02/11 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. /8) clk I/O clk Tn /8) I/O TOP - 1 ATmega32(L) OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 124 ...

Page 125

... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega32( WGM21 CS22 CS21 CS20 R/W ...

Page 126

... A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See 121 for more details. ATmega32(L) (1) “Fast PWM Mode” on page 120 (1) “Phase Correct PWM Mode” on page ...

Page 127

... T2S 1 0 clk /256 (From prescaler clk /1024 (From prescaler TCNT2[7:0] R/W R/W R/W R OCR2[7:0] R/W R/W R/W R ATmega32( TCNT2 R/W R/W R/W R OCR2 R/W R/W R/W R Table 127 ...

Page 128

... To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. 2503Q–AVR–02/ – – – – AS2 R ATmega32( TCN2UB OCR2UB TCR2UB ASSR When AS2 is I/O 128 ...

Page 129

... TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 2503Q–AVR–02/11 ATmega32(L) ) again becomes active, TCNT2 will read as the previous I/O 129 ...

Page 130

... PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. 2503Q–AVR–02/ OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R ATmega32( TOIE1 OCIE0 TOIE0 TIMSK R/W R/W R/W R TOV1 OCF0 TOV0 TIFR R/W R/W R/W R 130 ...

Page 131

... Additionally, clk T2S T2S ADTS2 ADTS1 ADTS0 – R/W R/W R ATmega32(L) 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S /8, clk T2S T2S as well as 0 (stop) may be selected. T2S ACME ...

Page 132

... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32 and peripheral devices or between several AVR devices. The ATmega32 SPI Peripheral includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...

Page 133

... For more details on automatic port overrides, refer to 54. Direction, Master SPI User Defined Input User Defined User Defined See “Alternate Functions of Port B” on page 57 direction of the user defined SPI pins. ATmega32(L) MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SCK SCK ...

Page 134

... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page ATmega32(L) 7. 134 ...

Page 135

... SPI_SlaveReceive ; Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page ATmega32(L) 7. 135 ...

Page 136

... When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. 2503Q–AVR–02/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R ATmega32( CPHA SPR1 SPR0 SPCR R/W R/W R 136 ...

Page 137

... Leading Edge 0 Sample 1 Setup SPR1 SPR0 ATmega32(L) for an example. The CPOL functionality is summa- Trailing Edge Falling Rising and Figure 68 for an example. The CPHA func- Trailing Edge Setup Sample SCK Frequency osc osc f ...

Page 138

... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega32 is also used for program memory and EEPROM download- ing or uploading. See SPI Data Register – SPDR ...

Page 139

... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega32(L) Trailing Edge SPI Mode Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 ...

Page 140

... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1 on page 2, Table 33 on page placement. ATmega32(L) Figure 69. CPU accessible I/O Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN ...

Page 141

... The XCK pin is only active when using Synchronous mode. Figure 70 2503Q–AVR–02/11 shows a block diagram of the clock generation logic. ATmega32(L) Figure 69) if the Buffer Registers are 141 ...

Page 142

... Input from XCK pin (Internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculating ATmega32(L) U2X / ...

Page 143

... BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps). System Oscillator clock frequency Figure 70 for details. depends on the stability of the system clock source therefore recommended to osc ATmega32(L) Equation for Calculating UBRR (1) Baud Rate Value f OSC ...

Page 144

... Bits inside brackets are (IDLE Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). An IDLE line must be high. ATmega32(L) Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 144 ...

Page 145

... even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity Data bit n of the character ATmega32(L) ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ...

Page 146

... UCSRC,r16 ret (1) /* Set baud rate */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); 1. See “About Code Examples” on page ATmega32(L) 7. 146 ...

Page 147

... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page ATmega32(L) 7. 147 ...

Page 148

... UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRB is static. (that is, only the TXB8 bit of the UCSRB Register is used after initialization). ATmega32(L) 148 ...

Page 149

... The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing Transmitter and pending transmissions are completed, that is, when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no lon- ger override the TxD pin. 2503Q–AVR–02/11 ATmega32(L) 149 ...

Page 150

... UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret (1) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page ATmega32(L) 7. 150 ...

Page 151

... Get status and 9th bit, then data */ /* from buffer */ status = UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page ATmega32(L) 7. 151 ...

Page 152

... The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. 2503Q–AVR–02/11 and “Parity Checker” on page 152. ATmega32(L) 152 ...

Page 153

... UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; 1. See “About Code Examples” on page IDLE ATmega32(L) 7. START Figure 73 BIT ...

Page 154

... Figure 75. For Double Speed mode the first low level must be delayed to (B). ATmega32(L) shows the sampling of the data bits and the parity BIT ...

Page 155

... D R (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104.35 ATmega32( ------------------------------------------ - D S ⋅ – ----------------------------------- ( ) for Normal Speed and for Normal Speed and M Max Total Recommended Max Error (%) Receiver Error (%) +6 ...

Page 156

... In this case an UBRR value that gives an acceptable low error can be used if possible. 2503Q–AVR–02/ (%) R (%) slow fast 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega32(L) Max Total Recommended Max Error (%) Receiver Error (%) +3.90/-4.00 ±1.5 +3.53/-3.61 ±1.5 +3.23/-3.30 ±1.0 156 ...

Page 157

... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. 2503Q–AVR–02/11 ATmega32(L) 157 ...

Page 158

... UCSRC,r16 ... (1) ... /* Set UBRRH UBRRH = 0x02; ... /* Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... 1. See “About Code Examples” on page ATmega32(L) 7. 158 ...

Page 159

... Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. See “About Code Examples” on page RXB[7:0] TXB[7:0] R/W R/W R/W R ATmega32( UDR (Read) UDR (Write) R/W R/W R/W R 159 ...

Page 160

... This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. 2503Q–AVR–02/ RXC TXC UDRE FE DOR R R ATmega32( U2X MPCM UCSRA R R R/W R 160 ...

Page 161

... The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char- acter Size frame the receiver and transmitter use. 2503Q–AVR–02/11 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN TXEN R/W R/W R/W R ATmega32(L) 157 UCSZ2 RXB8 TXB8 UCSRB R/W R 161 ...

Page 162

... This bit selects between Asynchronous and Synchronous mode of operation. Table 63. UMSEL Bit Settings 2503Q–AVR–02/ URSEL UMSEL UPM1 UPM0 R/W R/W R/W R section which describes how to access this register. UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega32( USBS UCSZ1 UCSZ0 UCPOL UCSRC R/W R/W R/W R “Accessing 162 ...

Page 163

... Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity USBS 0 1 UCSZ1 ATmega32(L) Stop Bit(s) 1-bit 2-bit UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit 163 ...

Page 164

... URSEL – – – UBRR[7: R R/W R/W R/W R section which describes how to access this register. ATmega32(L) Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge UBRR[11:8] UBRRH UBRRL R/W R/W R/W R/W R/W R/W R/W R ...

Page 165

... Error UBRR Error 0.2% 47 0.0% 0.2% 23 0.0% 0.2% 11 0.0% -3.5% 7 0.0% -7.0% 5 0.0% 8.5% 3 0.0% 8.5% 2 0.0% 8.5% 1 0.0% -18.6% 1 -25.0% 8.5% 0 0.0% – – – – – – 115.2 Kbps ATmega32(L) Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7.0% 7 ...

Page 166

... U2X = 1 U2X = 0 Error UBRR Error 0.0% 103 0.2% 0.0% 51 0.2% 0.0% 25 0.2% 0.0% 16 2.1% 0.0% 12 0.2% 0.0% 8 -3.5% 0.0% 6 -7.0% 0.0% 3 8.5% 0.0% 2 8.5% 0.0% 1 8.5% 0.0% 0 8.5% -7.8% 0 0.0% -7.8% – – – – – 250Kbps ATmega32( 7.3728MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0.0% 25 0.2% 23 0.0% 16 2.1% 15 0.0% 12 0.2% 11 0.0% 8 -3.5% 7 0.0% 6 -7.0% 5 0.0% 3 8.5% 3 0. ...

Page 167

... U2X = 1 U2X = 0 Error UBRR Error -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 1Mbps 691.2Kbps ATmega32(L) MHz f = 14.7456MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 0.0% 7 ...

Page 168

... U2X = 1 U2X = 0 Error UBRR Error 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – 2Mbps 1.152Mbps ATmega32( 20.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 0.0% 64 0.2% 79 0.0% 42 0.9% 59 0.0% 32 -1.4% 39 0.0% 21 -1.4% 29 0.0% 15 1.7% 19 0.0% 10 -1. ...

Page 169

... Device 1 Device 3 Device 2 Description The device that initiates and terminates a transmission. The master also generates the SCL clock. The device addressed by a master. The device placing data on the bus. The device reading data from the bus. ATmega32( ........ R1 R2 Device n 169 ...

Page 170

... START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. 2503Q–AVR–02/11 Figure 76, both bus lines are connected to the positive supply voltage through “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega32(L) 290. Two Data Stable 170 ...

Page 171

... NACK after the final byte. The MSB of the data byte is transmitted first. 2503Q–AVR–02/11 START STOP START Addr MSB 1 2 START ATmega32(L) REPEATED START STOP Addr LSB R/W ACK ...

Page 172

... Data MSB 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted Addr MSB Addr LSB R/W ACK START SLA+R/W ATmega32(L) Data LSB ACK STOP, REPEATED Data Byte START or Next Data MSB Data LSB ACK ...

Page 173

... SCL from Master A SCL from Master B SCL bus Line TB Masters Start Counting Low Period START SDA from Master A SDA from Master B SDA Line SCL Line ATmega32(L) TA high TB low high Masters Start Counting High Period Master A Loses Arbitration, SDA A SDA 173 ...

Page 174

... This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 2503Q–AVR–02/11 ATmega32(L) 174 ...

Page 175

... Address Match Unit Address Register (TWAR) Address Comparator SCL frequency Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table 119 on page 290 ATmega32(L) Figure 84. All registers drawn SDA Spike Filter Bit Rate Generator Prescaler ...

Page 176

... After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a slave • When a bus error has occurred due to an illegal START or STOP condition 2503Q–AVR–02/11 ATmega32(L) 176 ...

Page 177

... TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 R/W R/W R/W R for calculating bit rates TWINT TWEA TWSTA TWSTO TWWC R/W R/W R/W R ATmega32( TWBR2 TWBR1 TWBR0 TWBR R/W R/W R/W R “Bit Rate Generator TWEN – TWIE TWCR R R ...

Page 178

... This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Reserved Bit This bit is reserved and will always read as zero. 2503Q–AVR–02/ TWS7 TWS6 TWS5 TWS4 TWS3 ATmega32( – TWPS1 TWPS0 TWSR R R R/W R 178 ...

Page 179

... TWD7 TWD6 TWD5 TWD4 R/W R/W R/W R TWA6 TWA5 TWA4 TWA3 R/W R/W R/W R ATmega32(L) Prescaler Value 175. The value of TWPS1.. TWD3 TWD2 TWD1 TWD0 TWDR R/W R/W R/W R TWA2 TWA1 TWA0 TWGCE ...

Page 180

... SLA TWINT set. Status code indicates SLA+W sent, ACK received ATmega32(L) 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...

Page 181

... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. 2503Q–AVR–02/11 ATmega32(L) 181 ...

Page 182

... TWCR = (1<<TWINT) | (1<<TWEN); while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega32(L) Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits ...

Page 183

... TWINT Flag is set. The numbers in Table 74 to Table 77. Note that the prescaler bits are masked to zero in 86). In order to enter a Master mode, a START condition must be transmitted. The format Device 1 Device 2 MASTER SLAVE TRANSMITTER RECEIVER ATmega32( Device 3 ........ Device 183 ...

Page 184

... Application Software Response To TWCR To/from TWDR STO TWINT STA 0 1 Load SLA Load SLA Load SLA+R 0 ATmega32(L) TWWC TWEN – TWIE Table 74). In order to enter MT mode, TWWC TWEN – TWIE TWWC TWEN – ...

Page 185

... No TWDR action TWDR action TWDR action 1 ATmega32(L) X Data byte will be transmitted and ACK or NOT ACK will be received X Repeated START will be transmitted X STOP condition will be transmitted and TWSTO Flag will be Reset X STOP condition followed by a START condition will be ...

Page 186

... MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. 2503Q–AVR–02/ SLA W $ DATA From master to slave From slave to master 88). In order to enter a Master mode, a START condition must be transmitted. The format ATmega32(L) A DATA A P $ $20 ...

Page 187

... Received data can be read from the TWDR Register when the TWINT Flag TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA TWSTO Application Software Response To TWCR To/from TWDR STO TWINT STA ATmega32( ........ Device TWWC TWEN – TWIE Table 74). In order to enter MR mode, TWWC TWEN – TWIE X 1 ...

Page 188

... Other master A continues $68 $78 $B0 DATA From master to slave From slave to master n ATmega32(L) X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to masTer Transmitter mode X Two-wire Serial Bus will be released and not addressed ...

Page 189

... All the status codes mentioned in this section assume that the prescaler bits are zero Device 1 Device 2 SLAVE MASTER RECEIVER TRANSMITTER TWA6 TWA5 TWA4 Device’s Own Slave Address TWINT TWEA TWSTA ATmega32( Device 3 ........ Device n R1 TWA3 TWA2 TWA1 TWA0 TWSTO TWWC TWEN – ...

Page 190

... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 2503Q–AVR–02/11 ATmega32(L) 190 ...

Page 191

... No action ATmega32(L) TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned ...

Page 192

... From master to slave From slave to master 92). All the status codes mentioned in this section assume that the prescaler bits are zero Device 1 Device 2 SLAVE MASTER TRANSMITTER RECEIVER TWA6 TWA5 TWA4 Device’s Own Slave Address ATmega32(L) A DATA A DATA $60 $80 $80 $88 A $68 A DATA ...

Page 193

... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 2503Q–AVR–02/11 TWINT TWEA TWSTA TWSTO ATmega32(L) TWWC TWEN – TWIE Table 77. The ...

Page 194

... No TWDR action TWDR action TWDR action 1 ATmega32(L) TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...

Page 195

... From master to slave From slave to master n Application Software Response To TWCR To/from TWDR STO TWINT STA No TWDR action No TWCR action TWDR action 0 ATmega32(L) DATA A DATA $B8 $C0 A All 1's $C8 Any number of data bytes A and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus ...

Page 196

... Figure 95. An Arbitration Example SDA SCL 2503Q–AVR–02/11 Master Transmitter SLA+W A ADDRESS REPEATED START Transmitted from Master to Slave Device 1 Device 2 Device 3 MASTER SLAVE MASTER TRANSMITTER RECEIVER TRANSMITTER ATmega32(L) Master Receiver Rs SLA+R A DATA Transmitted from Slave to Master V CC ........ Device STOP R2 196 ...

Page 197

... Yes Write 68/78 Direction Read B0 ATmega32(L) Data STOP TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned ...

Page 198

... OUTPUT 1. See Table 80 on page 200. 2. Refer to Figure 1 on page 2 and Table 25 on page ADTS2 ADTS1 ADTS0 R/W R/W R “Analog Comparator Multiplexed Input” on page ATmega32(L) (2) for Analog Comparator pin placement – ACME PUD PSR2 PSR10 R R/W R/W R/W R 200 ...

Page 199

... Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set. 2503Q–AVR–02/ ACD ACBG ACO ACI ACIE R/W R/W R R/W R N/A 0 ATmega32( ACIC ACIS1 ACIS0 ACSR R/W R/W R 199 ...

Page 200

... Comparator Interrupt on Output Toggle 1 Reserved 0 Comparator Interrupt on Falling Output Edge 1 Comparator Interrupt on Rising Output Edge ADEN MUX2..0 Analog Comparator Negative Input x xxx AIN1 1 xxx AIN1 0 000 ADC0 0 001 ADC1 0 010 ADC2 0 011 ADC3 0 100 ADC4 0 101 ADC5 0 110 ADC6 0 111 ADC7 ATmega32(L) Table 200 ...

Related keywords