ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 33

• Manufacturer Part Number: ATmega32
• Manufacturer: Atmel Corporation

Specifications of ATmega32

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Idle Mode
ADC Noise
Reduction Mode
Power-down Mode
Power-save Mode
2503Q–AVR–02/11
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the
Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operat-
ing (if enabled). This sleep mode basically halts clk
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a Two-wire Serial Interface Address Match Interrupt, a Timer/Counter2 interrupt, an
SPM/EEPROM ready interrupt, an External level interrupt on INT0 or INT1, or an external inter-
rupt on INT2 can wake up the MCU from ADC Noise Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the External Oscillator is stopped, while the External interrupts, the
Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface
address match interrupt, an External level interrupt on INT0 or INT1, or an External interrupt on
INT2 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing oper-
ation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL fuses that define the
reset time-out period, as described in
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, that is, the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. The device can wake up from either Timer Overflow or Output Compare
event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK, and the Global Interrupt Enable bit in SREG is set.
If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended
instead of Power-save mode because the contents of the registers in the Asynchronous Timer
should be considered undefined after wake-up in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except clk
modules, including Timer/Counter2 if clocked asynchronously.
CPU
and clk
FLASH
“Clock Sources” on page
, while allowing the other clocks to run.
ASY
I/O
, allowing operation only of asynchronous
, clk
CPU
, and clk
25.
“External Interrupts” on page 66
ATmega32(L)
FLASH
, while allowing the
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