ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 225
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ATmega32
Manufacturer Part Number
ATmega32
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega32-16AC
Manufacturer:
COMPAL
Quantity:
500
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATmega32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega32-16PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
IEEE 1149.1
(JTAG)
Boundary-scan
Features
System Overview
Data Registers
Bypass Register
2503Q–AVR–02/11
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The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
Off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be
used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the
ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have
the AVR device in Reset during Test mode. If not reset, inputs to the device may be determined
by the scan operations, and the internal software may be in an undetermined state when exiting
the Test mode. Entering reset, the outputs of any Port Pin will instantly enter the high impedance
state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be
issued to make the shortest possible scan chain through the device. The device can be set in
the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruc-
tion with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
The Data Registers relevant for Boundary-scan operations are:
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The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
Supports the Optional IDCODE Instruction
Additional Public AVR_RESET Instruction to Reset the AVR
Bypass Register
Device Identification Register
Reset Register
Boundary-scan Chain
ATmega32(L)
225