ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 178
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ATmega32
Manufacturer Part Number
ATmega32
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega32-16AC
Manufacturer:
COMPAL
Quantity:
500
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATmega32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega32-16PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
TWI Status Register –
TWSR
2503Q–AVR–02/11
is detected, and then generates a new START condition to claim the bus Master status. TWSTA
must be cleared by software when the START condition has been transmitted.
• Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-
matically. In slave mode, setting the TWSTO bit can be used to recover from an error condition.
This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed
slave mode and releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is
low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to
one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the
slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI
transmissions are terminated, regardless of any ongoing operation.
• Bit 1 – Reserved Bit
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-
vated for as long as the TWINT Flag is high.
• Bits [7:3] – TWS: TWI Status
These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different sta-
tus codes are described later in this section. Note that the value read from TWSR contains both
the 5-bit status value and the 2-bit prescaler value. The application designer should mask the
prescaler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Reserved Bit
This bit is reserved and will always read as zero.
Bit
Read/Write
Initial Value
TWS7
R
7
1
TWS6
R
6
1
TWS5
R
5
1
TWS4
4
R
1
TWS3
R
3
1
R
2
–
0
TWPS1
R/W
1
0
ATmega32(L)
TWPS0
R/W
0
0
TWSR
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