ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 72
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ATmega32
Manufacturer Part Number
ATmega32
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega32-16AC
Manufacturer:
COMPAL
Quantity:
500
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATmega32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega32-16PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Force Output
Compare
Compare Match
Blocking by TCNT0
Write
Using the Output
Compare Unit
Compare Match
Output Unit
2503Q–AVR–02/11
The OCR0 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled
the CPU will access the OCR0 directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0) bit. Forcing compare match will not set the
OCF0 Flag or reload/clear the timer, but the OC0 pin will be updated as if a real compare match
had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled).
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized
to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the output compare unit, inde-
pendently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals
the OCR0 value, the compare match will be missed, resulting in incorrect waveform generation.
Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.
The setup of the OC0 should be performed before setting the Data Direction Register for the port
pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare
(FOC0) strobe bits in Normal mode. The OC0 Register keeps its value even when changing
between waveform generation modes.
Be aware that the COM01:0 bits are not double buffered together with the compare value.
Changing the COM01:0 bits will take effect immediately.
The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses
the COM01:0 bits for defining the Output Compare (OC0) state at the next compare match. Also,
the COM01:0 bits control the OC0 pin output source.
the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the fig-
ure are shown in bold. Only the parts of the general I/O port Control Registers (DDR and PORT)
that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference
is for the internal OC0 Register, not the OC0 pin. If a System Reset occur, the OC0 Register is
reset to “0”.
Figure 30
shows a simplified schematic of
ATmega32(L)
72