ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 19

• Manufacturer Part Number: ATmega32
• Manufacturer: Atmel Corporation

Specifications of ATmega32

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

The EEPROM Address
Register – EEARH and
EEARL
The EEPROM Data
Register – EEDR
The EEPROM Control
Register – EECR
2503Q–AVR–02/11
• Bits 15..10 – Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bits 9..0 – EEAR9..0: EEPROM Address
The EEPROM Address Registers
1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
1023. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7..4 – Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
R
–
7
0
7
0
7
–
0
EEAR6
R/W
R/W
14
R
X
R
–
6
0
6
0
6
–
0
EEAR5
R/W
R/W
13
R
R
–
5
0
X
5
0
5
–
0
–
EEARH and EEARL – specify the EEPROM address in the
EEAR4
R/W
R/W
12
–
4
R
0
X
4
0
4
–
R
0
EEAR3
EERIE
R/W
R/W
R/W
11
R
X
–
3
0
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
10
R
X
–
2
0
2
0
2
0
EEAR9
EEAR1
EEWE
R/W
R/W
R/W
R/W
X
9
1
0
1
0
1
X
ATmega32(L)
EEAR8
EEAR0
EERE
R/W
R/W
LSB
R/W
R/W
8
0
X
X
0
0
0
0
EEARH
EEARL
EEDR
EECR
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