DSPIC30F4011-20I/P Microchip Technology, DSPIC30F4011-20I/P Datasheet
DSPIC30F4011-20I/P
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DSPIC30F4011-20I/P Summary of contents
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... Modes of Operation ..................................................................................................... 35-8 35.4 Master Mode Clock Frequency .................................................................................. 35-21 35.5 Operation in Power-Saving Modes ............................................................................ 35-22 35.6 Special Function Registers Associated with the SPI1 Module................................... 35-23 35.7 Related Application Notes.......................................................................................... 35-24 35.8 Revision History ......................................................................................................... 35-25 © 2008 Microchip Technology Inc. 35 DS70272B-page 35-1 ...
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... Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1RXB SPI1BUF Read SPI1BUF DS70272B-page 35-2 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPI1TXB Write SPI1BUF 16 Internal Data Bus 1:1/4/16/64 Primary F CY Prescaler SPI1CON1<1:0> SPI1CON1<4:2> Enable Master Clock © 2008 Microchip Technology Inc. ...
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... This technique double buffers transmit and receive operations and allows continuous data transfers in the background. Transmission and reception occur simultaneously. In addition, there is a 16-bit shift register, SPI1SR, that is not memory mapped used for shifting data in and out of the SPI port. © 2008 Microchip Technology Inc. 35 DS70272B-page 35-3 ...
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... U-0 U-0 U-0 — — — Clearable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 — bit 8 U-0 R-0 R-0 — SPITBF SPIRBF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Note 1: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains cleared if MSTEN = 0. 2: The CKE bit is not used in the Framed SPI modes. The user application should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2008 Microchip Technology Inc. R/W-0 R/W-0 ...
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... The CKE bit is not used in the Framed SPI modes. The user application should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). Legend Readable bit -n = Value at POR DS70272B-page 35 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2008 Microchip Technology Inc. ...
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... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application Legend Readable bit -n = Value at POR © 2008 Microchip Technology Inc. U-0 U-0 U-0 U-0 — — ...
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... DS70272B-page 35-8 PROCESSOR 2 (SPI Slave) SDI1 SDO1 Serial Receive Buffer (SPI1RXB) SDI1 SDO1 Shift Register (SPI1SR) MSb Serial Transmit Buffer (SPI1TXB) Serial Clock SCK1 SCK1 SPI1 Buffer (SPI1BUF) (2) SS1 SS1 SSEN (SPI1CON1<7> and MSTEN (SPI1CON1<5> LSb (1) © 2008 Microchip Technology Inc. ...
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... SPITBF (SPI1STAT<1>) bit is clear. The write can occur while SPI1SR is shifting out the previously written data, allowing continuous transmission. Note: The SPI1SR register cannot be written into directly by the user application. All writes to the SPI1SR register are performed through the SPI1BUF register. © 2008 Microchip Technology Inc. 35 DS70272B-page 35-9 ...
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... Mode Enabled //Enable SPI Module //Write data to be transmitted //Interrupt Controller Settings //Clear the Interrupt Flag //Enable the Interrupt © 2008 Microchip Technology Inc. ...
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... SDI1 and input sample are shown for two different values of the SMP (SPI1CON1<9>) bit for demonstration purposes only. Only one of the two configurations of the SMP bit can be chosen during operation. 4: Operation for 8-bit mode is shown. Except for the number of clock pulses, the 16-bit mode is similar. © 2008 Microchip Technology Inc. User application writes new (1) ...
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... Idle clock state to active clock state //Idle state for clock is a low level; active //state is a high level //Master Mode disabled //No Receive Overflow Has Occurred //Enable SPI Module //Interrupt Controller Settings //Clear the Interrupt Flag //Enable The Interrupt © 2008 Microchip Technology Inc. ...
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... Two SPI1 Clock modes are shown only to demonstrate CKP (SPI1CON1<6>) and CKE (SPI1CON1<8>) bit functionality. Any combination of CKP and CKE bits can be selected for module operation there are no pending transmissions or a transmission is in progress, SPI1BUF is transferred to SPI1SR as soon as the user application writes to SPI1BUF. © 2008 Microchip Technology Inc. (1) bit 6 bit 2 ...
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... Slave mode. 3: Transmit data is held in SPI1TXB and SPITBF remains set until all bits are transmitted. DS70272B-page 35-14 (1) bit 5 bit 4 bit 6 bit 3 bit 2 bit 1 bit 0 bit 0 1 instruction cycle latency SPI1SR to SPI1BUF User application reads SPI1BUF © 2008 Microchip Technology Inc. ...
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... FRMPOL (SPI1CON2<13>) selects the polarity of the frame synchronization pulse (active-high or active-low) for a single SPI data frame. • FRMDLY (SPI1CON2<1>) selects whether the synchronization pulse coincides with or precedes the first serial clock pulse. © 2008 Microchip Technology Inc. (1) bit 6 bit 2 bit 5 ...
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... SPI1BUF before the frame synchronization pulse is received. Note: Receiving a frame synchronization pulse will start a transmission regardless of whether data was written to SPI1BUF write was performed, the old contents of the SPI1TXB will be transmitted. DS70272B-page 35-16 © 2008 Microchip Technology Inc. ...
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... Write to SPI1BUF Figure 35-9: SPI Master, Frame Master Timing (FRMDLY = 1) SCK1 (CKP = 1) SCK1 (CKP = 0) SS1 (FRMPOL = 1) SS1 (FRMPOL = 0) SDO1 SDI1 Write to SPI1BUF © 2008 Microchip Technology Inc. SDO1 SDI1 SDI1 SDO1 Serial Clock SCK1 SCK1 SS1 SS1 Frame Synchronization Pulse bit 15 bit 14 ...
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... SS1 SS1 Frame Synchronization Pulse bit 15 bit 14 bit 15 bit 14 Sample SS1 pin for Pulse bit 15 bit 14 bit 15 bit 14 Pulse Generated by SS1; Receive Samples at SDI1 PROCESSOR 2 bit 13 bit 12 bit 13 bit 12 Receive Samples at SDI1 bit 13 bit 12 bit 13 bit 12 © 2008 Microchip Technology Inc. ...
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... SPI clock. When SS1 is sampled at its active state, data will be transmitted on the appropriate transmit edge of SCK1. Figure 35-14: SPI Slave, Frame Slave Connection Diagram dsPIC30F (SPI1 Slave, Framed Slave) © 2008 Microchip Technology Inc. SDO1 SDI1 SDI1 SDO1 Serial Clock ...
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... The SPI1 Interrupt Flag, SPI1IF, is set whenever the SPIROV, SPIRBF (SPI1STAT<0>) or SPITBF (SPI1STAT<1>) bits are set. The interrupt flag cannot be cleared by hardware and must be reset in software. The actual SPI1 interrupt is generated only when the corresponding SPI1IE bit is set in the IEC0 Control register. DS70272B-page 35-20 © 2008 Microchip Technology Inc. ...
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... Table 35-1: Sample SCK1 Frequencies MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: SCK1 frequencies are shown in kHz. © 2008 Microchip Technology Inc. SPI Clock Frequency SCK Primary Prescaler * Secondary Prescaler (1) Secondary Prescaler Settings 1:1 2:1 ...
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... Idle mode. If SPISIDL = 1, the SPI1 module will stop communication on entering Idle mode. It will operate in the same manner as it does in Sleep mode. If SPISIDL = 0 (default selection), the module will continue operation in Idle mode. DS70272B-page 35-22 © 2008 Microchip Technology Inc. ...
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Special Function Registers Associated with the SPI1 Module Table 35-2: SPI1 Register Map SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SPI1CON2 ...
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... PICmicro Microcontroller Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the dsPIC30F SMPS and Digital Power Conversion device family. DS70272B-page 35-24 Microcontroller Application Note # AN1006 AN746 AN719 © 2008 Microchip Technology Inc. ...
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... This revision incorporates the following content updates: • Registers: - SPI1CON1: SPI1 Control Register 1 (see Register 35-2) – Note 1 has been added in the register. • Additional minor corrections such as language and formatting updates are incorporated in the entire document. © 2008 Microchip Technology Inc. 35 DS70272B-page 35-25 ...
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... Family Reference Manual NOTES: DS70272B-page 35-26 © 2008 Microchip Technology Inc. ...