DSPIC30F4011-20I/P Microchip Technology, DSPIC30F4011-20I/P Datasheet
DSPIC30F4011-20I/P
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DSPIC30F4011-20I/P Summary of contents
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... Family Silicon Errata and Data Sheet Clarification The dsPIC30F4011/4012 family devices that you have received conform functionally to the current Device Data Sheet (DS70135F), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number CPU MAC Class 1. Instructions with ±4 Address Modification CPU 2. DAW.b Instruction I/O SFR Writes 3. PSV — 4. Operations CPU Nested DO 5. Loops PLL 4x Mode 6. Interrupt — 7. Controller CPU 8. DISI Instruction Output PWM Mode 9 ...
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... When Timer Gated Accumulation is enabled, and an external signal is applied, the POSCNT increments and generates an interrupt after a match with MAXCNT. If the ADC module enabled state when the device enters Sleep Mode, the power-down current (I device may exceed the device data sheet specifications. dsPIC30F4011/4012 Affected (1) Revisions ...
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... Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A4). 1. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using ± ...
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... Microchip Technology Inc. dsPIC30F4011/4012 These instructions are identified in Table 3. Example 2 demonstrates one scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F4011/4012 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... Module: CPU When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler ...
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... SET_AND_SAVE_CPU_IPL (save_to RESTORE_CPU_IPL (save_to) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Work around 2: For C Language Source Code For applications using the C language, MPLAB C30 versions 1.32 and higher provide several macros for modifying the CPU IPL. The SET_CPU_IPL macro provides the ability to safely modify the CPU IPL, as shown in Example 6 ...
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... For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used. This macro disables interrupts before executing the desired expression, as shown in Example 8. This macro is not distributed with the compiler. EXAMPLE 8: USING INTERRUPT_PROTECT MACRO #define INTERRUPT_PROTECT ( int save_sr; \ SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void) 0; ...
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... © 2010 Microchip Technology Inc. dsPIC30F4011/4012 9. Module: Output Compare If the desired duty cycle is ‘0’ (OCxRS = 0), the module will generate a high level glitch The second problem is that on the next cycle after the glitch, the OC pin does not go high other words, it misses the next compare for any value written on OCxRS ...
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... Module: ADC ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate an interrupt after a certain number of INT0 triggered conversions, the ADC conversions will not be triggered and the device will remain in Sleep ...
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... IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Work around To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. In addition, a global variable could be used to keep track of bit 15, so that when an overflow or underflow condition is present on POSCNT, the variable will toggle bit 15 ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... © 2010 Microchip Technology Inc. dsPIC30F4011/4012 21. Module: PLL The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. Work around The user application must include an oscillator failure trap service routine. In the trap service routine, first inspect the status of the Clock Failure Status bit (OSCCON< ...
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... Module 10-bit Addressing mode, some address matches do not set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: • ...
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... Work around 1: Use program Flash memory instead of data EEPROM to store constant data. Work around 2: Use less than 16 bits in each word in the available word of data EEPROM, excluding the Most Significant bit. FIGURE 1: dsPIC30F4011/4012 DATA EEPROM High Byte (Odd Address) 0x7FFC01 0x7FFC03 B 0x7FFC05 0x7FFC07 ...
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... Module: OSC2 Pin The port pin, RC15, is multiplexed with the primary oscillator pin, OSC2. When pin RC15 is required for digital input/output, specific bits in the Oscillator Configuration register, FOSC, may be set up as follows: • FOS<2:0> bits (FOSC<10:8>) configured for LP, LPRC, FRC, ECIO, ERCIO or ECIO w/PLL 4x/8x/16x • ...
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... Symbol Characteristic No. V Input Low Voltage IL DI19 SDA, SCL V Input High Voltage IH DI29 SDA, SCL © 2010 Microchip Technology Inc. dsPIC30F4011/4012 specifica- IL Standard Operating Conditions: 3.3V and 5.0V (±10%) (unless otherwise stated) Operating temperature Min Typ Max V — 0.8 SS 2.1 — ...
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... This document replaces the following errata documents: • DS80205, “dsPIC30F4011/4012 Rev. A1 Silicon Errata” • DS80215, “dsPIC30F4011/4012 Rev. A2/A3 Silicon Errata” • DS80398, “dsPIC30F4011/4012 Rev. A4 Silicon Errata” Rev B Document (8/2009) Updated silicon issue 7 (Interrupt Controller). Added silicon issues 30 (QEI) and 31 (QEI). ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 01/05/10 ...