ATMEGA329-16AU Atmel, ATMEGA329-16AU Datasheet - Page 389

• Manufacturer Part Number: ATMEGA329-16AU
• Description: IC AVR MCU 32K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 54
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2552K–AVR–04/11
23 LCD Controller ..................................................................................... 228
24 JTAG Interface and On-chip Debug System ..................................... 245
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 251
26 Boot Loader Support – Read-While-Write Self-Programming ......... 278
22.4
22.5
22.6
22.7
23.1
23.2
23.3
23.4
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
24.10
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
26.1
26.2
26.3
26.4
26.5
Prescaling and Conversion Timing ................................................................214
Changing Channel or Reference Selection ...................................................216
ADC Conversion Result .................................................................................221
Register Description ......................................................................................223
Features ........................................................................................................228
Mode of Operation .........................................................................................231
LCD Usage ....................................................................................................235
Register Description ......................................................................................239
Features ........................................................................................................245
Overview ........................................................................................................245
Test Access Port – TAP ................................................................................245
TAP Controller ...............................................................................................247
Using the Boundary-scan Chain ....................................................................248
Using the On-chip Debug System .................................................................248
On-chip Debug Specific JTAG Instructions ...................................................249
Using the JTAG Programming Capabilities ...................................................250
Bibliography ...................................................................................................250
Register Description ......................................................................................250
Features ........................................................................................................251
System Overview ...........................................................................................251
Data Registers ...............................................................................................251
Boundary-scan Specific JTAG Instructions ...................................................253
Boundary-scan Related Register in I/O Memory ...........................................254
Boundary-scan Chain ....................................................................................255
ATmega329/3290/649/6490 Boundary-scan Order .......................................264
Boundary-scan Description Language Files ..................................................277
Features ........................................................................................................278
Application and Boot Loader Flash Sections .................................................278
Read-While-Write and No Read-While-Write Flash Sections ........................278
Boot Loader Lock Bits ...................................................................................281
Entering the Boot Loader Program ................................................................282
ATmega329/3290/649/6490
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