ATMEGA329V-8AU Atmel, ATMEGA329V-8AU Datasheet - Page 182
ATMEGA329V-8AU
Manufacturer Part Number
ATMEGA329V-8AU
Description
IC AVR MCU 32K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA329-16AU.pdf
(30 pages)
2.ATMEGA329-16AU.pdf
(392 pages)
3.ATMEGA329V-8AU.pdf
(375 pages)
Specifications of ATMEGA329V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
1K Bytes
Input Output
54
Interface
SPI/UART/USART/USI
Memory Type
Flash
Number Of Bits
8
Package Type
100-pin TQFP
Programmable Memory
32K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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UBRRnL and UBRRnH –
USART Baud Rate Registers n
182
ATmega329/3290/649/6490
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 82. USBSn Bit Settings
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
Table 83. UCSZ Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOLn bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK).
Table 84. UCPOLn Bit Settings
Bit
Read/Write
Initial Value
UCPOLn
UCSZn2
0
0
0
0
1
1
1
1
0
1
R/W
15
R
–
7
0
0
USBSn
0
1
R/W
14
R
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
–
6
0
0
UCSZn1
R/W
13
R
–
5
0
0
0
0
1
1
0
0
1
1
R/W
12
R
–
4
0
0
UBRRn[7:0]
Stop Bit(s)
1-bit
2-bit
R/W
R/W
11
3
0
0
UCSZn0
0
1
0
1
0
1
0
1
R/W
R/W
10
UBRRn[11:8]
2
0
0
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
9
1
0
0
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
R/W
R/W
8
0
0
0
2552H–AVR–11/06
UBRRnH
UBRRnL
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