PIC18LF2610-I/SP Microchip Technology, PIC18LF2610-I/SP Datasheet - Page 26
![IC MCU FLASH 32KX16 28SDIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2610-I/SP
Manufacturer Part Number
PIC18LF2610-I/SP
Description
IC MCU FLASH 32KX16 28SDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18LF2410-ISO.pdf
(376 pages)
3.PIC18LF2410-ISO.pdf
(8 pages)
4.PIC18F2515-ISO.pdf
(16 pages)
5.PIC18F2515-ISO.pdf
(6 pages)
6.PIC18F2515-ISO.pdf
(8 pages)
Specifications of PIC18LF2610-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3968 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Data Rom Size
3968 B
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC18F2221-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18F2515-ISO PDF datasheet #4
- PIC18F2515-ISO PDF datasheet #5
- PIC18F2515-ISO PDF datasheet #6
- Current page: 26 of 376
- Download datasheet (7Mb)
PIC18F2X1X/4X1X
2.6
The PIC18F2X1X/4X1X devices include an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s
clock source. This may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 22.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 32).
2.6.1
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs F
• In INTIO2 mode, OSC1 functions as RA7 and
2.6.2
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.
2.6.3
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
DS39636D-page 28
while OSC1 functions as RA7 for digital input and
output.
OSC2 functions as RA6, both for digital input and
output.
Internal Oscillator Block
INTIO MODES
INTOSC OUTPUT FREQUENCY
OSCTUNE REGISTER
OSC
/4,
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTRC clock will reach the new frequency within
8 clock cycles (approximately 8 * 32 μs = 256 μs). The
INTOSC clock will stabilize within 1 ms. Code execu-
tion continues during this shift. There is no indication
that the shift has occurred.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in Internal Oscillator modes.
2.6.4
The 4x frequency multiplier can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those
internal Oscillator modes where the PLL is available. In
all other modes, it is forced to ‘0’ and is effectively
unavailable.
2.6.5
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as V
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed.
discussed in Section 2.6.5.1 “Compensating with
the USART”, Section 2.6.5.2 “Compensating with
the Timers” and Section 2.6.5.3 “Compensating
with the CCP Module in Capture Mode”, but other
techniques may be used.
Three
PLL IN INTOSC MODES
INTOSC FREQUENCY DRIFT
DD
or temperature changes, which can
compensation
© 2009 Microchip Technology Inc.
techniques
are
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