PIC24HJ64GP510-I/PF Microchip Technology, PIC24HJ64GP510-I/PF Datasheet - Page 220

IC PIC MCU FLASH 32KX16 100TQFP

PIC24HJ64GP510-I/PF

Manufacturer Part Number
PIC24HJ64GP510-I/PF
Description
IC PIC MCU FLASH 32KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510-I/PF

Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
No. Of Pwm Channels
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ64GP510-I/PF
Manufacturer:
Microchip
Quantity:
602
Part Number:
PIC24HJ64GP510-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24HJXXXGPX06/X08/X10
21.2
All of the PIC24HJXXXGPX06/X08/X10 devices power
their core digital logic at a nominal 2.5V. This may cre-
ate an issue for designs that are required to operate at
a higher typical voltage, such as 3.3V. To simplify sys-
tem
PIC24HJXXXGPX06/X08/X10 family incorporate an
on-chip regulator that allows the device to run its core
logic from V
The regulator provides power to the core from the other
V
than 5 ohms) capacitor (such as tantalum or ceramic)
be connected to the V
This helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Table 24-13 of Section 24.1 “DC Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 21-1:
DS70175H-page 218
Note 1:
DD
Note:
pins. The regulator requires that a low-ESR (less
2:
On-Chip Voltage Regulator
design,
C
,
STARTUP
it takes approximately 20 μs for the on-chip
EFC
These are typical operating voltages. Refer to
TABLE 24-13: “Internal Voltage Regulator
Specifications” located in Section 24.1 “DC
Characteristics” for the full operating ranges
of V
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
DD
CAP
CAP
.
DD
3.3V
/V
/V
and V
DDCORE
DDCORE
is applied every time the device
all
CAP
ON-CHIP VOLTAGE
REGULATOR
CONNECTIONS
CAP
V
V
V
DD
CAP
SS
pin.
/V
PIC24H
STARTUP
/V
pin.
DDCORE
/V
DDCORE
DDCORE
devices
, code execution is
.
pin (Figure 21-1).
(1)
in
the
21.3
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the reg-
ulated voltage V
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to exces-
sive current draw when a large inductive load is turned
on).
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If
TPWRT = 0 and a crystal oscillator is being used, then
a nominal delay of TFSCM = 100 is applied. The total
delay in this case is TFSCM.
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should VDD fall below the BOR threshold volt-
age.
BOR: Brown-out Reset
CAP
/V
DDCORE
© 2009 Microchip Technology Inc.
. The main purpose of

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