ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 297
![MCU AVR 128K ISP FLASH 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA1284P-AU
Manufacturer Part Number
ATMEGA1284P-AU
Description
MCU AVR 128K ISP FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Rom Size
4 KB
Height
1.05 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
10.1 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
748
Part Number:
ATMEGA1284P-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 297 of 581
- Download datasheet (27Mb)
8272A–AVR–01/10
Table 26-4.
Note:
Table 26-5.
Note:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Fuse High Byte
OCDEN
JTAGEN
SPIEN
WDTON
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See
3. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allow the system clock to be output on PORTB1. See
4. See
(3)
(4)
(4)
(3)
290
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
See
page 31
on page 39
Fuse High Byte
Fuse Low Byte
for details.
”WDTCSR – Watchdog Timer Control Register” on page 60
”System and Reset Characteristics” on page 335
”System Clock Prescaler” on page 40
for details.
Bit No
Bit No
for details.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
Description
Enable OCD
Enable JTAG
Enable Serial Program and Data
Downloading
Watchdog Timer always on
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
details)
Select Boot Size (see
details)
Select Reset Vector
for details.
Table 26-9
Table 26-9
for details.
for
for
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
1 (unprogrammed)
Default Value
1 (unprogrammed, OCD
disabled)
0 (programmed, JTAG enabled)
0 (programmed, SPI prog.
enabled)
1 (unprogrammed)
1 (unprogrammed, EEPROM
not preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
for details.
Table 25-10 on page
”Clock Output Buffer”
(2)
(2)
(1)
(2)
(2)
(2)
(1)
(2)
Table 8-1 on
297
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