ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 377

• Manufacturer Part Number: ATMEGA1284P-PU
• Description: MCU AVR 128K ISP FLASH 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8059D–AVR–11/09
21 ADC - Analog-to-digital Converter ..................................................... 240
22 JTAG Interface and On-chip Debug System ..................................... 260
23 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 266
24 Boot Loader Support – Read-While-Write Self-Programming ......... 276
20.1Overview .............................................................................................................237
20.2Analog Comparator Multiplexed Input .................................................................237
20.3Register Description ............................................................................................238
21.1Features ..............................................................................................................240
21.2Overview .............................................................................................................240
21.3Operation .............................................................................................................241
21.4Starting a Conversion ..........................................................................................242
21.5Prescaling and Conversion Timing ......................................................................243
21.6Changing Channel or Reference Selection .........................................................246
21.7ADC Noise Canceler ...........................................................................................248
21.8ADC Conversion Result ......................................................................................253
21.9Register Description ............................................................................................255
22.1Features ..............................................................................................................260
22.2Overview .............................................................................................................260
22.3TAP – Test Access Port ......................................................................................260
22.4TAP Controller .....................................................................................................262
22.5Using the Boundary-scan Chain ..........................................................................263
22.6Using the On-chip Debug System .......................................................................263
22.7On-chip Debug Specific JTAG Instructions .........................................................264
22.8Using the JTAG Programming Capabilities .........................................................264
22.9Bibliography .........................................................................................................265
22.10Register Description ..........................................................................................265
23.1Features ..............................................................................................................266
23.2Overview .............................................................................................................266
23.3Data Registers .....................................................................................................267
23.4Boundary-scan Specific JTAG Instructions .........................................................268
23.5Boundary-scan Chain ..........................................................................................269
23.6ATmega1284P Boundary-scan Order .................................................................272
23.7Boundary-scan Description Language Files ........................................................274
23.8Register Description ............................................................................................275
24.1Features ..............................................................................................................276
ATmega1284P
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