PIC18F4220-I/ML Microchip Technology, PIC18F4220-I/ML Datasheet - Page 16
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PIC18F4220-I/ML
Manufacturer Part Number
PIC18F4220-I/ML
Description
IC MCU FLASH 2KX16 EEPROM 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-I/ML
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
PIC18FX220/X320
3.4
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a Data Latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, loading EEDATA with the
data to be written and initiating a memory write by
appropriately configuring the EECON1 and EECON2
registers. A byte write automatically erases the location
and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort and this
must be done prior to initiating a write sequence.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h,
and then 0AAh, immediately prior to asserting the WR
bit in order for the write to occur. The write sequence is
initiated by setting the WR bit (EECON1<1> = 1). It is
strongly recommended that the WREN bit be set only
when absolutely necessary.
The write will begin on the falling edge of the 4th PGC
after the WR bit is set.
After the programming sequence terminates, PGC must
still be held low for the time specified by parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-8:
DS39592F-page 16
PGC
PGD
4-Bit Command
Data EEPROM Programming
1
0
2
0
3
0
4
0
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
2
15 16
P5A
4-Bit Command
1
0
2
0
3
0
4
0
PGD = Input
P5
1
0
Data Payload
2
0
16-Bit
FIGURE 3-7:
15 16
0
0
P5A
4-Bit Command
1
0
2
0
3
No
0
4
0
Unlock Sequence
for Write to Occur
0AAh – EECON2
Delay P11 + P10
PROGRAM DATA FLOW
55h – EECON2
2010 Microchip Technology Inc.
Enable Write
Set Address
Start Write
Sequence
Set Data
Data EEPROM
Done?
Done
Start
Write Time
P11
Yes
P11
Data Payload
16-Bit
1
n
2
n