PIC18F4220-I/ML Microchip Technology, PIC18F4220-I/ML Datasheet - Page 5
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PIC18F4220-I/ML
Manufacturer Part Number
PIC18F4220-I/ML
Description
IC MCU FLASH 2KX16 EEPROM 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-I/ML
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
2.3
The code memory space extends from 0000h to 1FFFh
(8 Kbytes) in a single 8-Kbyte panel. Addresses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Panel 1. All code
memory is on-chip.
A user may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
TABLE 2-2:
FIGURE 2-7:
2010 Microchip Technology Inc.
PIC18F1220
PIC18F2220
PIC18F4220
PIC18F1320
PIC18F2320
PIC18F4320
3FFFFEh
3FFFFFh
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
300000h
300001h
300002h
300003h
Memory Map
Device
IMPLEMENTATION OF CODE MEMORY
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
ID Location 6
ID Location 7
ID Location 8
MEMORY MAP FOR PIC18FX220/X320
CONFIG1H
CONFIG2H
Device ID 1
Device ID 2
CONFIG1L
CONFIG2L
Code Memory Size (Bytes)
0000h-0FFFh (4K)
0000h-0FFFh (4K)
0000h-0FFFh (4K)
0000h-1FFFh (8K)
0000h-1FFFh (8K)
0000h-1FFFh (8K)
3FFFFFh
200000h
07FFh
0FFFh
17FFh
1FFFh
0000h
200h
Locations 300001h through 30000Dh are reserved
for the Configuration Words. These Words may be
set to select various device options and are
described in Section 5.0 “Configuration Word”.
These Configuration Words read out normally, even
after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
Device ID Words. These Words may be used by the
programmer to identify what device type is being
programmed and are described in Section 5.0
“Configuration Word”. These Configuration Words
read out normally, even after code protection.
Unimplemented
PIC18FX320
Read as ‘0’s
PIC18FX220/X320
Boot Block
8 Kbytes
Block 0
Block 1
Block 2
Block 3
Data EEPROM Size (Bytes)
000-0FFh (256)
000-0FFh (256)
000-0FFh (256)
000-0FFh (256)
000-0FFh (256)
000-0FFh (256)
Unimplemented
PIC18FX220
Read as ‘0’s
Boot Block
4 Kbytes
Block 0
Block 1
DS39592F-page 5