AT89C5131A-S3SUM Atmel, AT89C5131A-S3SUM Datasheet - Page 16

• Manufacturer Part Number: AT89C5131A-S3SUM
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Package: 52PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.3.2
5.3.3
16
AT89C5130A/31A-M
PLL Programming
Divider Values
Figure 5-4.
The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.
The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is
enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Figure 5-5.
To generate a 48 MHz clock using the PLL, the divider values have to be configured following
the oscillator frequency. The typical divider values are shown in
Table 5-1.
Oscillator Frequency
PLL Filter Connection
PLL Programming Flow
Typical Divider Values
12 MHz
16 MHz
18 MHz
20 MHz
24 MHz
3 MHz
6 MHz
8 MHz
PLLF
Configure Dividers
Programming
PLL Locked?
N3:0 = xxxxb
R3:0 = xxxxb
LOCK = 1?
Enable PLL
PLLEN = 1
R+1
16
12
8
6
4
3
8
2
PLL
VSS
R
C1
VSS
C2
N+1
1
1
1
1
1
3
5
1
Table
5-1.
PLLDIV
B4h
F0h
70h
50h
30h
20h
72h
10h
4337K–USB–04/08