DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 18
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DSPIC30F5011-20I/PT
Manufacturer Part Number
DSPIC30F5011-20I/PT
Description
IC DSPIC MCU/DSP 66K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F5011-20IPT.pdf
(220 pages)
2.DSPIC30F5011-20IPT.pdf
(16 pages)
3.DSPIC30F5011-20IPT.pdf
(6 pages)
4.DSPIC30F5011-20IPT.pdf
(14 pages)
5.DSPIC30F5011-20IPT.pdf
(26 pages)
Specifications of DSPIC30F5011-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
52
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F5011-20I/PTG
DSPIC30F501120/PT
DSPIC30F501120IPT
DSPIC30F501120IPT
DSPIC30F501120/PT
DSPIC30F501120IPT
DSPIC30F501120IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F5011/5013
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
• DIVF - 16/16 signed fractional divide
• DIV.sd - 32/16 signed divide
• DIV.ud - 32/16 unsigned divide
• DIV.sw - 16/16 signed divide
• DIV.uw - 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion as shown in
get instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
TABLE 2-2:
DS70116J-page 18
DIVF
DIV.sd
DIV.sw or DIV.s
DIV.ud
DIV.uw or DIV.u
Note:
Instruction
Divide Support
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Table 2-2
DIVIDE INSTRUCTIONS
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
(REPEAT will execute the tar-
2.4
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform
inherent
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow archi-
tecture; therefore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction (e.g.,
ED, EDAC).
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for AccA (SATA)
• Automatic saturation on/off for AccB (SATB)
• Automatic saturation on/off for writes to data
• Accumulator Saturation mode selection
A block diagram of the DSP engine is shown in
Figure
TABLE 2-1:
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY.N
MSC
Function
memory (SATDW)
(ACCSAT)
Note:
Instruction
2-2.
DSP Engine
accumulator-to-accumulator
For CORCON layout, see
DSP INSTRUCTION
SUMMARY
No change in A
A = A + (x – y)
A = A + (x * y)
A = A – x * y
Operation
A = (x – y)
Algebraic
A = A + x
A = – x * y
A = x * y
© 2011 Microchip Technology Inc.
A = 0
2
2
2
Table
ACC WB?
operations,
Yes
Yes
Yes
Yes
No
No
No
No
No
3-3.