DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 78

• Manufacturer Part Number: DSPIC30F5011-20I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5011-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5011-20I/PTG; DSPIC30F501120/PT; DSPIC30F501120IPT; DSPIC30F501120IPT

dsPIC30F5011/5013
12.1.2
Each capture channel has an associated FIFO buffer
which is four 16-bit words deep. There are two status
flags which provide status on the FIFO buffer:
• ICBFNE – Input Capture Buffer Not Empty
• ICOV – Input Capture Overflow
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic ‘1’. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured until all four events have been
read from the buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
12.1.3
The input capture module consists of up to 8 input cap-
ture channels. Each channel can select between one of
two timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
12.1.4
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the fol-
lowing operations are performed by the input capture
logic:
• The input capture interrupt flag is set on every
• The interrupt on Capture mode setting bits,
• A capture overflow condition is not generated in
DS70116J-page 78
edge, rising and falling.
ICI<1:0>, is ignored since every capture
generates an interrupt.
this mode.
CAPTURE BUFFER OPERATION
TIMER2 AND TIMER3 SELECTION
MODE
HALL SENSOR MODE
12.2
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
Independent of the timer being enabled, the input cap-
ture module will wake-up from the CPU Sleep or Idle
mode when a capture event occurs if ICM<2:0> = 111
and the interrupt enable bit is asserted. The same wake-
up can generate an interrupt if the conditions for pro-
cessing the interrupt have been satisfied. The wake-up
feature is useful as a method of adding extra external pin
interrupts.
12.2.1
CPU Sleep mode allows input capture module opera-
tion with reduced functionality. In the CPU Sleep mode,
the ICI<1:0> bits are not applicable and the input cap-
ture module can only function as an external interrupt
source.
The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111) in order for the
input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.
12.2.2
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the Inter-
rupt mode selected by the ICI<1:0> bits is applicable,
as well as the 4:1 and 16:1 capture prescale settings
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover,
the ICSIDL bit must be asserted to a logic ‘0’.
If
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin will serve only as an external interrupt pin.
12.3
The input capture channels have the ability to generate
an interrupt based upon the selected number of cap-
ture events. The selection number is set by control bits
ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx Status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IEC Control register.
the
Input Capture Operation During
Sleep and Idle Modes
Input Capture Interrupts
input
INPUT CAPTURE IN CPU SLEEP
MODE
INPUT CAPTURE IN CPU IDLE
MODE
capture
© 2011 Microchip Technology Inc.
module
is
defined
as