PIC32MX440F512H-80I/MR Microchip Technology, PIC32MX440F512H-80I/MR Datasheet - Page 39

IC PIC MCU FLASH 512KX32 64-QFN

PIC32MX440F512H-80I/MR

Manufacturer Part Number
PIC32MX440F512H-80I/MR
Description
IC PIC MCU FLASH 512KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX440F512H-80I/MR

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
17.3
An example of a high-level algorithm for calculating the
checksum for a PIC32 device is illustrated in Figure 17-1
to demonstrate one method to derive a checksum. This
is merely an example of how the actual calculations can
be accomplished, the method that is ultimately used is
left to the discretion of the software developer.
As stated earlier, the PIC32 checksum is calculated as
the 32-bit summation of all bytes (8-bit quantities) in
program
Configuration Words), the Device ID register with
applicable mask, and the device Configuration Words
with applicable masks.
FIGURE 17-1:
© 2010 Microchip Technology Inc.
Read Program Flash, Boot Flash (including DEVCFG
Algorithm
Apply DEVCFG and DEVID masks to appropriate
Checksum (32-bit quantity) = 2’s complement
Flash,
registers) and DEVID register in tempBuffer
tmpChecksum (32-bit quantity) = 0
bytes (8-bit quantities) in
locations in tempBuffer
boot
Finish processing all
HIGH-LEVEL ALGORITHM FOR CHECKSUM CALCULATION
pic32_checksum
of tmpChecksum
tempBuffer?
Flash
Done
Yes
(except
device
No
tmpChecksum = tempChecksum + Current Byte Value
Next, the 2’s complement of the summation is
calculated. This final 32-bit number is presented as the
checksum.
The mask values of the device Configuration and
Device ID registers are derived as described in the
previous section, 17.2 “Mask Values”.
Another noteworthy point is that the last four 32-bit
quantities in boot Flash are the device Configuration
registers. An arithmetic AND operation of these device
Configuration register values is performed with the
appropriate mask value, before adding their bytes to
the checksum.
Similarly, an arithmetic AND operation of the Device ID
register is performed with the appropriate mask value,
before adding its bytes to the checksum.
(8-bit quantity) in tmpBuffer
PIC32MX
DS61145G-page 39

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