DSPIC30F5011-30I/PT Microchip Technology, DSPIC30F5011-30I/PT Datasheet
DSPIC30F5011-30I/PT
Specifications of DSPIC30F5011-30I/PT
DSPIC30F501130IPT
Available stocks
Related parts for DSPIC30F5011-30I/PT
DSPIC30F5011-30I/PT Summary of contents
Page 1
... Rev. A3 Silicon Errata The dsPIC30F5011/5013 (Rev. A3) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70116 – “dsPIC30F5011, dsPIC30F5013 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
Page 2
... DISI Instruction The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the decrements to zero. 12. Output Compare Module in PWM Mode Output compare will produce a glitch when loading 0% duty cycle in PWM mode. It will also miss the next compare after the glitch. ...
Page 3
... MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed ...
Page 4
... Example 2 is demonstrated in Example 3. DS80223H-page 4 These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F5011/5013 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
Page 5
... Note: For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 5. Module – Read Operations on I2CCON SFR Data read from the I2CCON Special Function Register (SFR) may not be correct at device operation greater than 20 MIPS for V range of 4 ...
Page 6
... Module – Write Operations on I2CTRN SFR Data writes to the I2CTRN Special Function Register (SFR) may not be correct at device operation greater than 20 MIPS for V range of 4.5V to 5.5V (or 10 MIPS 3.6V). If the dsPIC DSC device needs to operate at a throughput higher than 20 MIPS, the user should incorporate the suggested work around while writing to the I2CTRN SFR ...
Page 7
... X; \ DISICNT = 0; } DISI_PROTECT(SRbits.IPL = 0x5); © 2008 Microchip Technology Inc. dsPIC30F5011/5013 10. Module: Interrupt Controller – Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...
Page 8
... Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from The counter is loaded with 7 at the end of the DISI instruction. ...
Page 9
... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 11 demonstrates the work around described above would apply to a dsPIC30F5011 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function ...
Page 10
... Work around 2: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing consumption of the device. Similarly, instead of ...
Page 11
... Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT ...
Page 12
... Module there are two I C devices on the bus, one of them is acting as the Master receiver and the other as the Slave transmitter. If both devices are config- ured for 10-bit addressing mode, and have the same value in the A10 and A9 bits of their ...
Page 13
... For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 C module is that have 2 ...
Page 14
... APPENDIX A: REVISION HISTORY Revision A (1/2005) Original version of the document. Revision B (3/2005) Added silicon issues 8 (PLL) and 9 (Interrupt Controller – Sequential Interrupts). Revision C (4/2005) Added silicon issue 10 (Using OSC2/RC15 pin for Digital I/O). Revision D (9/2006) Added errata 1, 11, 12, 13, 15 and 16. ...
Page 15
... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 16
... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...