PIC16LF874-04I/PQ Microchip Technology, PIC16LF874-04I/PQ Datasheet - Page 72

• Manufacturer Part Number: PIC16LF874-04I/PQ
• Description: IC PIC MCU FLASH 4KX14 44MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF874-04I/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F87X
9.1.1
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
FIGURE 9-2:
DS30292C-page 70
SCK (CKP = 0,
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
SDI (SMP = 0)
SDI (SMP = 1)
SSPIF
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
MASTER MODE
SPI MODE TIMING, MASTER MODE
bit7
bit7
bit7
bit6
bit5
bit4
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit3
CY
)
bit2
CY
CY
)
)
2001 Microchip Technology Inc.
bit1
bit0
bit0
bit0