AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 499
![MCU ARM7 64K HS FLASH 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7L64-AU
Manufacturer Part Number
AT91SAM7L64-AU
Description
MCU ARM7 64K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7L64-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxx
No. Of I/o's
80
Ram Memory Size
6KB
Cpu Speed
36MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 499 of 564
- Download datasheet (9Mb)
34.5.2.5
Figure 34-7.
34.5.2.6
6257A–ATARM–20-Feb-08
-
-
2
1
2
1
2
1
1
2
/
/
/
/
/
/
/
/
3
3
3
3
3
3
3
3
-V
V
V
V
V
V
V
V
V
V
V
V
GND
GND
GND
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Low Power Waveform
Frame Rate
Default and Low Power Waveform
Frame
To reduce toggle activity and hence power consumption, a low power waveform can be selected
by writing LPMODE to one. The default and low power waveform is shown in
duty and 1/3 bias. For other selections of duty and bias, the effect is similar.
Note:
The Frame Rate register (SLCDC_FRR) enables the generation of the frequency used by the
SLCD Controller. It is done by a prescaler (division by 8, 16, 32, 64, 128, 256, 512 and 1024) fol-
lowed by a finer divider (division by 1, 2, 3, 4, 5, 6, 7 or 8).
To calculate the proper frame frequency needed, the equation below must be taken into
account:
Where:
f
f
PRES = prescaler value (8, 16, 32, 64, 128, 256, 512 or 1024)
DIV = divider value (1, 2, 3, 4, 5, 6, 7, or 8)
NCOM = depends of number of commons and is defined in
SCLK
frame
= frame frequency
= slow clock frequency
Frame
Refer to the LCD specification to verify that low power waveforms are supported.
SEG0
COM0
SEG0 - COM0
f
frame
AT91SAM7L128/64 Preliminary
-
-
2
1
2
1
2
1
1
2
/
/
/
/
/
/
/
/
3
3
3
3
3
3
3
3
-V
=
V
V
V
V
V
V
V
V
V
V
V
GND
GND
GND
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
--------------------------------------------------------- -
(
PRES DIV NCOM
⋅
Frame
fSCLK
⋅
Table 34-3
Frame
)
below:
SEG0
COM0
SEG0 - COM0
Figure 34-7
for 1/3
499
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